• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.4
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• pp.508-514
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• 2020

To implement the continuously evolving mobile communication standards such as Long Term Evolution (LTE) and 5G, the Software Defined Radio (SDR) concept provides great flexibility and efficiency. For many years, a high-end Digital Signal Processor (DSP) System on Chip (SoC) has been developed to support multicore and various hardware coprocessors. This paper introduces the implementation of the SDR platform hardware using TI's TCI663x chip. Using the platform, LTE transport channel is implemented by interworking multicore DSP with Bit rate Coprocessor (BCP) and Turbo Decoder Coprocessor (TCP) and the performance is evaluated according to various implementation options. In order to evaluate the performance of the implemented LTE transport channel, LTE base station system was constructed by combining FPGA main board for physical channels, SDR platform board, and RF & Antenna board.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Korea Society of Computer and Information
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• v.16 no.11
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• pp.1-8
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• 2011

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

• Journal of information and communication convergence engineering
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• v.6 no.4
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• pp.376-382
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• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.2
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• pp.201-206
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• 2007

In this paper, we propose the efficient low power test methodology of NoC(Network-on chip) for the test of core-based systems that use this platform. To reduce the power consumption of transferring data through router channel, the scan vectors are partitioned into flits by channel width. The don't cares in unspecified scan vectors are mapped to binary values to minimize the switching rate between flits. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method leads to about 35% reduction in test power.

• ETRI Journal
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• v.28 no.4
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• pp.525-528
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• 2006

In this letter, we present a design of a single chip video decoder called advanced mobile video ASIC (A-MoVa) for mobile multimedia applications. This chip uses a mixed hardware/software architecture to improve both its performance and its flexibility. We designed the chip using a partition between the hardware and software blocks, and developed the architecture of an H.264 decoder based on the system-on-a-chip (SoC) platform. This chip contains 290,000 logic gates, 670,000 memory gates, and its size is $7.5\;mm{\times}7.5\;mm$ (using 0.25 micron 4-layers metal CMOS technology).

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.697-707
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• 2007

Since embedded software is very dependent for target hardware architecture, characteristics of the platform must be considered when designing the software. Furthermore, MPSoCs consists of heterogeneous hardware components that are specified in micro level. Thus mapping of embedded software for MPSoCs should be considered the characteristics. In this paper, we provide an approach to automatic mapping PIM (Platform Independent Model) of an embedded software to PSM(Platform Specific Model) for MPSoC(Multi Processor System On Chip) and verify its effectiveness with simulation. In the proposed approach, tasks are derived from an object oriented model based on the UML (Unified Modeling Language). And then the types of the derived tasks are identified. With the identified types and inter relationship between tasks, the tasks are assigned to appropriate heterogeneous hardware components. We expect that the approach improve accuracy of the assigning and concurrency of the deployed software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.106-114
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• 2010

We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evolution to overcome a verification gap. The proposed platform includes a high level synthesis, and we develop a power-aware verification platform for low power design and verification automation using it's results. We developed a verification automation and power-aware verification methodology based on control and data flow graph (CDFG) and an abstract level language and RTL. The verification platform includes self-checking and the coverage driven verification methodology. Especially, the number of the random vector decreases minimum 5.75 times with the constrained random vector algorithm which is developed for the power-aware verification. This platform can verify a low power design with a general logic simulator using a power and power cell modeling method. This unified design and verification platform allow automatically to verify, design and synthesis the giga-scale design from the system level to RTL level in the whole design flow.

• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.