• Title/Summary/Keyword: chip control

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Integration of Current-mode VSFD with Multi-valued Weighting Function

  • Go, H.M.;Takayama, J.;Ohyama, S.;Kobayashi, A.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.921-926
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    • 2003
  • This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

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Design of Space Vector Modulation PWM and Digital Control of System On Programmable-Chip Using FPGA (FPGA를 이용한 공간벡터 변조 PWM 및 디지털 제어부의 System On Programmable Chip 설계)

  • Hwang, Jeong-Won;Kim, Seung-Ho;Yang, Bin;Lee, Cheon-Gi;Park, Seung-Yub
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.61 no.1
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    • pp.47-54
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    • 2012
  • This paper presents implementation of SVPWM technique for three phase Voltage Source Inverter using FPGA. Software-based vector-control calculations much this drawback, in order to improve the hardware-vector-control tries. Without the need for additional software, vector control algorithm is designed to be modular SOPC, and DSP will reduce most of the operations. In this paper, the SVPWM that using HDL for the AC motor vector control algorithm level, and the dead time part and the speed control in order to controled a speed detector and designed in the form of modules. Then ALTERA corporation Cyclone III series EP3C16F484 can be verified by implemented.

Characteristics of Indium-Tin-Oxide Electrode for Continuous-flow PCR Chip (연속흐름 중합효소연쇄반응칩 제작을 위한 인듐 산화막 전극의 특성분석)

  • Joung, Seung-Ryong;Kim, Jun-Hyeok;Yi, In-Je;Kang, C.J.;Kim, Yong-Sang
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.3
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    • pp.561-565
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    • 2007
  • We propose glass and PDMS (polydimethylsiloxane) chips for DNA amplification with continuous-flow PCR (polymerase chain reaction). The PDMS microchannel was fabricated using a negative molding method for sample injection. Three heaters and sensors of ITO (indium-tin-oxide) thin films were fabricated on glass chip. ITO heaters and sensors were calibrated accurately for the temperature control of the liquid flow. ITO heater generated stable heat versus applied power. ITO sensor resistance was changed linearly versus temperature increase as a RTD (resistance temperature detector) sensor. As a result, we enable precision temperature control of continuous-flow PCR chip. Using the continuous-flow PCR chip DNA plasmid pKS-GFP 720 bp was successfully amplified.

Design of a Neurochip's Core with on-chip Learning Capability on Hardware with Minimal Global Control (On-chip 학습기능을 구현한 최소 광역 제어 신경회로망 칩의 코어 설계)

  • 배인호;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.10
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    • pp.161-172
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    • 1994
  • This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

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A software-controlled bandwidth allocation scheme for multiple router on-chip-networks

  • Bui, Phan-Duy;Lee, Chanho
    • Journal of IKEEE
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    • v.23 no.4
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    • pp.1203-1207
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    • 2019
  • As the number of IP cores has been increasing in a System-on-Chip (SoC), multiple routers are included in on-chip-networks. Each router has its own arbitration policy and it is difficult to obtain a desired arbitration result by combining multiple routers. Allocating desired bandwidths to the ports across the routers is more difficult. In this paper, a guaranteed bandwidth allocation scheme using an IP-level QoS control is proposed to overcome the limitations of existing local arbitration policies. Each IP can control the priority of a packet depending on the data communication requirement within the allocated bandwidth. The experimental results show that the proposed mechanism guarantees for IPs to utilize the allocated bandwidth in multiple router on-chip-networks. The maximum error rate of bandwidth allocation of the proposed scheme is only 1.9%.

Design and Implementation of Providing Conditional Access Broadcasting Service System (수신 제한된 방송 서비스 제공 시스템 설계 및 구현)

  • Kim, Dong-Ok;Shin, Ik-Ryong
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.8 no.2
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    • pp.64-71
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    • 2009
  • In this paper, This thesis is cell phone for make CAS service be for hand joining broadcasting Create a way CAS Chip. PerSam issue card inside use Seed Key and algorithm make CID Key and record CAS Chip. PerSam member Card inside use Seed Key and algorithm make Subscriber Key after include Subscriber. Key CAS Chip for record CID Key register EMM. make CAS CHIP in accordance with issue CAS Chip. broadcast service entry be for hand treatment so make low bandwidth for joining massage and make increase a member.

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Development of Simulator based on Object-Oriented Programming for Chip Mounter Using Stochastic Petri Nets (확률 페트리 네트를 이용한 객체지향 기반의 표면 실장기 시뮬레이터 개발)

  • 박기범;박태형
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.57-57
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    • 2000
  • The purpose of this paper is show that an chip mounter can be modeled by stochastic petri nets, and that the simulator to verify a fitness of the program to assemble. The chip mounter can be constructed by using the petri net class (CPetriNet) based on the object-oriented programming. By using this simulator, we can get the information about the description of motion of the chip mounter, and moreover, we can evaluate the productivity.

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Chip Form Prediction using Fuzzy Logic in Turning (절삭가공에서 퍼지알고리즘을 이용한 칩형상 예측)

  • Choi, Won-Sik
    • Journal of the Korean Society of Industry Convergence
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    • v.4 no.2
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    • pp.127-132
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    • 2001
  • In turning, the chip may be produced in the form of continuous chip or discontinuous chip. The continuous chips are dangerous to the operator and difficult to be handled at high speed machining. The signal of AE(Acoustic Emission) is found out to be related to cutting conditions, tool materials, test conditions and tool geometry in turning. In this study, the relationship between AE signal and chip form was experimentally investigated. The experimental results show that the types of chip form are possible to be classified from the AE signal using fuzzy logic.

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Realization of a Remote Management System for Process Inspection of Chip-Mounter

  • Lim, Sun-Jong;Joon Lyon
    • 제어로봇시스템학회:학술대회논문집
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    • 2002.10a
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    • pp.91.4-91
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    • 2002
  • Today, Internal offers WWW(World Wide Web), remote control, file transfer and e-mail service. Among the services, WWW takes large portion because of convenient GUI, easy information search and unlimited information registration. WWW service gives the comfort in life such as goods purchase, information search, real-time news, internet TV and medical diagnosis. Remote Monitoring Server(RMS) Ssystem that uses internet and WWW is constructed for chip mounter. Hardware base consists of RMS, chip mounter and C/S(Customer Service) service. Software includes DBMS and various modules in server home page. Web browser provide product num her, bad product number, troubl...

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Design of FIR System and Hilbert Transformer Having Ability of Selecting Filter Length (필터 Length를 가변할 수 있는 FIR 디지털 필터 및 힐버트 변환기의 설계)

  • Kim, Se-Jung;Hwang, Ho-Jung
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.567-570
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    • 1988
  • This paper describes the design of FIR filtering DSP-chip that can be operated without programming. The proposed DSP-chip has not only the improvement of execution time but also selectivity of filter length from N=1 to N=128. Hilbert Transformer can be designed from this chip. FIR filter system is composed of Data memory/Control Unit, external memory and multiplier-accumulator. Data memory/Control Unit is laid out in this paper.

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