• Journal of Institute of Control, Robotics and Systems
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• v.8 no.6
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• pp.514-523
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• 2002

Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• Journal of the Korean Society for Precision Engineering
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• v.7 no.2
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• pp.85-94
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• 1990

In automatic metal cuttings, the chip control is one of the serious problems. So the automatic detection of chip forms is essential to the chip control in automatic metal cuttings. Cutting experiments were carried out under the variety of cutting conditions (cutting speed, feed, depth of cut and tool geometry) and with workpiece made of steel (S45C), and cutting forces were measured in-processing by using a piezoelectric type Tool Dynamometer. In this report, the frequency analysis of dynamic components, the upper frequency distributions, the ratio of RMS values, the numbers of null point and the probability density were calculated from the dynamic componeents of cutting forces filtered through various band pass filters. Experimental results showed that computer chip form monitoring system based on the cutting forces was designed and simulated and that 6 type of chip forms could be detected while in-process machining.

• Journal of the Korean Society for Precision Engineering
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• v.5 no.1
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• pp.84-93
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• 1988

The on-line detection of the chip flow is one of the most important technologies in com- pletly automatic operation of machine tool, such as FMS and Unmanned Factories. This problem has been studied by many researchers, however, it is not solved as yet. For the recognition of chip flow in this study, the dynamic cutting force components due to the chip breaking were measured by dynamometer of piezo-electric type, and the frequency components of cutting force were also analyzed. From the measured results, the effect of cutting conditions and tool geometry on the dynamic cutting force component and chip formation were investigated in addition to the relationships between frequency of chip breaking (fB) and side serrated crack (fC) of chip. As a result, the following conclusions were obtaianed. 1) The chip formations have a large effect on the dynamic cutting force components. When chip breaking takes place, the dynamic cutting force component greatly increases, and the peridoic components appear, which correspond to maximum peak- frequency. 2) The crater wear of tool has a good effect on the chip control causing the chiup to be formed as upward-curl shape. In this case, the dymamic cutting force component greatly increases also 3) fB and fC of chip are closely corelated, and fC of chips has a large effect on the change of the situation of chip flow and dynamic cutting force component. 4) Under wide cutting conditions, the limit value (1.0 kgf) of dynamic cutting force component exists between the broken and continuous chips. Accordingly, this value is suitable for recognition of chip flow in on-line control of the cutting process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.284-287
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• 2001

In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

• Journal of Bio-Environment Control
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• v.1 no.1
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• pp.61-71
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• 1992

This study is performed to develop an automatic irrigation control of system for effective water management in greenhouse. The automatic irrigation control system is composed of an IR-RED optical sensor in tensiometer and an One-chip micro controller. The following results are obtained : 1. A practical IR-RED optical sensor in tensiometer, which shows the starting point of irrigation, was developed. 2. The automatic irrigation system with the optical sensor and One-chip micro controller was developed and also designed to be able to combine with the control system for temperature, curtain opening, etc. 3. A multiple irrigation control system for several greenhouses were suggested. 4. The results of the system test with the driving program for automatic water management were excellent.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1286-1288
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• 1996

An add/drop control chip for SDH transmission system has been designed in AT&T 0.5um CMOS ORCA FPGA. This device plays an important role in achieving self-healing ring operation which protects against failure. After this device receives each 24-ch AU-3 signals from the west, east, and add parts, it outputs each 24-ch switched signals through the control data of system control port. This device consists of eight sub-part such west/east transmitting part, west/east receiving part, add/drop control part, AIS control part, and CPU interface part. The designed device is capable to ring networks as well as linear networks.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.12
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• pp.2926-2935
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• 1993

Chip breaker selection analysis, only being possible through experimental process, was obtained by a applied equation which used an orthogonal cutting model and a basic chip deformation. This equation could present an analysis of the chip breaking phenomena without the use of an actual experimetal method, and it was applied to computer simulation and proved the validity of theory through actual experiments. From these results, an efficient method for finding the optimum conditions of chip breaking was found through an optimized theory being applied to basic program. A finite element model for simulating chip breaking in orthogonal cutting was developed and discussed. By simulation the animation of chip breaking is observed in process on the computer screen.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.415-418
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• 2005

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed feature from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.253-256
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• 2001

This paper describes a high speed MAC(Media Access Control) function chip for IEEE 802.11 MAC layer protocol. The MAC chip has control registers and interrupt scheme for interface with CPU and deals with transmission/reception of data as a unit of frame. The developed MAC chip is composed of protocol control block, transmission block, and reception block which supports the BCF function in IEEE 802.11 specification. The test suite which is adopted in order to verify operation of the MAC chip includes various functions, such as RTS-CTS frame exchange procedure, correct IFS(Inter Frame Space)timing, access procedure, random backoff procedure, retransmission procedure, fragmented frame transmission/reception procedure, duplicate reception frame detection, NAV(Network Allocation Vector), reception error processing, broadcast frame transmission/reception procedure, beacon frame transmission/reception procedure, and transmission/reception FIEO operation. By using this technique, it is possible to reduce the load of CPU and firmware size in high speed wireless LAN system.