• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Agricultural and Biosystems Engineering
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• v.4 no.1
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• pp.8-15
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• 2003

In Korea, quality evaluation of dried oak mushrooms are done first by classifying them into more than 10 different categories based on the state of opening of the cap, surface pattern, and colors. And mushrooms of each category are further classified into 3 or 4 groups based on its shape and size, resulting into total 30 to 40 different grades. Quality evaluation and sorting based on the external visual features are usually done manually. Since visual features of mushroom affecting quality grades are distributed over the entire surface of the mushroom, both front (cap) and back (stem and gill) surfaces should be inspected thoroughly. In fact, it is almost impossible for human to inspect every mushroom, especially when they are fed continuously via conveyor. In this paper, considering real time on-line system implementation, image processing algorithms utilizing artificial neural network have been developed for the quality grading of a mushroom. The neural network based image processing utilized the raw gray value image of fed mushrooms captured by the camera without any complex image processing such as feature enhancement and extraction to identify the feeding state and to grade the quality of a mushroom. Developed algorithms were implemented to the prototype on-line grading and sorting system. The prototype was developed to simplify the system requirement and the overall mechanism. The system was composed of automatic devices for mushroom feeding and handling, a set of computer vision system with lighting chamber, one chip microprocessor based controller, and pneumatic actuators. The proposed grading scheme was tested using the prototype. Network training for the feeding state recognition and grading was done using static images. 200 samples (20 grade levels and 10 per each grade) were used for training. 300 samples (20 grade levels and 15 per each grade) were used to validate the trained network. By changing orientation of each sample, 600 data sets were made for the test and the trained network showed around 91 % of the grading accuracy. Though image processing itself required approximately less than 0.3 second depending on a mushroom, because of the actuating device and control response, average 0.6 to 0.7 second was required for grading and sorting of a mushroom resulting into the processing capability of 5,000/hr to 6,000/hr.

• Journal of Internet Computing and Services
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• v.9 no.6
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• pp.1-13
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• 2008

Trusted Computing is a hardware-based technology that aims to guarantee security for machines beyond their users' control by providing security on computing hardware and software. TPM(Trusted Platform Module), the trusted platform specified by the Trusted Computing Group, acts as the roots for the trusted data storage and the trusted reporting of platform configuration. Data sealing encrypts secret data with a key and the platform's configuration at the time of encryption. In contrast to the traditional data sealing based on binary hash values of the platform configuration, a new approach called property-based data sealing was recently suggested. In this paper, we propose and analyze a new property-based data sealing protocol using the weakest precondition concept by Dijkstra. The proposed protocol resolves the problem of system updates by allowing sealed data to be unsealed at any configuration providing the required property. It assumes practically implementable trusted third parties only and protects platform's privacy when communicating. We demonstrate the proposed protocol's operability with any TPM chip by implementing and running the protocol on a software TPM emulator by Strasser. The proposed scheme can be deployed in PDAs and smart phones over wireless mobile networks as well as desktop PCs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.360-369
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• 2008

The solar cells should be operated at the maximum power point because its output characteristics were greatly fluctuated on the variation of insolation, temperature and load. It is necessary to install an inverter among electric power converts by means of the output power of solar cell is DC. The inverter is operated supply a sinusoidal current and voltage to the load and the interactive utility line. In this paper, the proposes a photovoltaic system is designed with a step up chopper and single phase PWM voltage source inverter. Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper is operated in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature for solar cell has typical dropping character. The single phase PWM voltage source inverter is consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be develop continuously by connecting with the source of electric power for ordinary using. It can be cause the efect of saving electric power, from 10 to 20%. The single phase PWM voltage source inverter operates in situation, that its output voltage is in same phase with the utility voltage. The inverter are supplies an ac power with high factor and low level of harmonics to the load and the utility power system.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.239-240
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• 2012

With advancements in semiconductor device technologies, manufacturing processes are getting more complex and it became more difficult to maintain tighter process control. As the number of processing step increased for fabricating complex chip structure, potential fault inducing factors are prevail and their allowable margins are continuously reduced. Therefore, one of the key to success in semiconductor manufacturing is highly accurate and fast fault detection and classification at each stage to reduce any undesired variation and identify the cause of the fault. Sensors in the equipment are used to monitor the state of the process. The idea is that whenever there is a fault in the process, it appears as some variation in the output from any of the sensors monitoring the process. These sensors may refer to information about pressure, RF power or gas flow and etc. in the equipment. By relating the data from these sensors to the process condition, any abnormality in the process can be identified, but it still holds some degree of certainty. Our hypothesis in this research is to capture the features of equipment condition data from healthy process library. We can use the health data as a reference for upcoming processes and this is made possible by mathematically modeling of the acquired data. In this work we demonstrate the use of recurrent neural network (RNN) has been used. RNN is a dynamic neural network that makes the output as a function of previous inputs. In our case we have etch equipment tool set data, consisting of 22 parameters and 9 runs. This data was first synchronized using the Dynamic Time Warping (DTW) algorithm. The synchronized data from the sensors in the form of time series is then provided to RNN which trains and restructures itself according to the input and then predicts a value, one step ahead in time, which depends on the past values of data. Eight runs of process data were used to train the network, while in order to check the performance of the network, one run was used as a test input. Next, a mean squared error based probability generating function was used to assign probability of fault in each parameter by comparing the predicted and actual values of the data. In the future we will make use of the Bayesian Networks to classify the detected faults. Bayesian Networks use directed acyclic graphs that relate different parameters through their conditional dependencies in order to find inference among them. The relationships between parameters from the data will be used to generate the structure of Bayesian Network and then posterior probability of different faults will be calculated using inference algorithms.

• Journal of Digital Convergence
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• v.14 no.4
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• pp.419-424
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• 2016

In this paper, we studied a light distribution for the LED chips arrangement using an optical design software. The structures of the edge type LED luminaires are reflector plane, LGP(lighting guide plane) and diffuse plane. The reflector plane is on the middle of the overall structure. We had simulation that placing LED chips on the reflector center of the reflector edge by changing the position of LED chips above the reflector center at 1mm, 2mm, and 3mm respectively. In the case, when LED chips are on the center of the reflector, it shows the light distribution of the general diffuse illumination, the semi-direct distribution with 0.56 efficiency and the direct distribution with 0.31 efficiency. And the wedge type LGP shows more efficiency than the flat type. Gradually increasing shape of semi-spherical type by 0.015mm has power of 1.02W, efficiency of 0.25, and maximum luminous intensity of 0.104W/sr, it also and shows the better optical characteristics than the reflector plane that have no patterns. This semi-spherical type shows the better optical characteristics than the reflector plane that have no patterns.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.510-515
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• 1997

Packaging takes an extremely important element of optical module cost due primarily to the added complication of alignment between semiconductor devices and optical fiber, and many efforts have been devoted on reducing the cost by eliminating the complicated optical alignment procedures in passive manner. In this study, we fabricated silicon optical benches on which the optical alignments are accomplished passively. To improve the positioning accuracy of a flip-chip bonded LD, we adopted fiducial marks and solder dams which are self-aligned with V-groove etch patterns, and a stand-off to control the height and to improve the heat dissipation of LD. Optical sub-assemblies exhibited an average efficiency of -11.75$\pm$1.75 dB(1$\sigma$) from the LD-to-single mode fiber coupling and an average sensitivity of -35.0$\pm$1.5 dBm from the fiber and photodetector coupling.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.36-42
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• 2010

FFT(Fast Fourier Transform) processor is one of the key components in the implementation of OFDM systems for many wireless standards such as IEEE 802.22. To improve the performances of FFT processors, various studies have been carried out to reduce the complexities of multipliers, memory interface, control schemes and so on. While the number of FFT stages increases logarithmically $log_2N$) as the FFT point-size (N) increases, the number of required registers (or, memories) increases linearly. In large point-size FFT designs, the registers occupy more than 70% of the chip area. In this paper, to reduce the memory size of IFFT for OFDM transmitters, we propose a new IFFT design method based on a combined mapping of modulated data, pilot and null signals. The proposed method focuses on reducing the sizes of the registers in the first two stages of the IFFT architectures since the first two stages require 75% of the total registers. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 38.5% area reduction compared with previous IFFT designs.

• Korean Journal of Acupuncture
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• v.23 no.3
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• pp.133-160
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• 2006

Objectives : Scolopendrae Corpus has a broad array of clinical applications in Korean medicine, including treatment of inflammatory conditions such as arthritis. To explore the global gene expression profiles in human Raw cell lines treated with Scolopendrae Corpus herbal-acupuncture solution (SCHAS), cDNA microarray analysis was performed. Methods : The Raw 264.7 cells were treated with lipopolysaccharide (LPS), SCHAS, or both. The primary data was normalized by the total spots of intensity between two groups, and then normalized by the intensity ratio of reference genes such as housekeeping genes in both groups. The expression ratio was converted to log2 ratio. Normalized spot intensities were calculated into gene expression ratios between the control and treatment groups. Greater than 2 fold changes between two groups were considered to be of significance. Results : Of the 8 K genes profiled in this study, with a cut-off level of two-fold change in the expression, 20 genes (BCL2-related protein A1, MARCKS-like 1, etc.) were upregulated and 5 genes (activated RNA polymerase II transcription cofactor 4, calcium binding atopy-related autoantigen 1, etc.) downregulated following LPS treatment. 139 genes (kell blood group precursor (McLeod phenotype), ribosomal protein S7, etc.) were upregulated and 42 genes (anterior gradient 2 homolog (xenopus laevis), phosphodiesterase 8B, etc.) were downregulated following SCHAS treatment. And 10 genes (yeast saccharomyces cerevisiae intergeneic sequence 4-1, mitogen-activated protein kinase 1, etc.) were upregulated and 8 genes (spermatid perinuclear RNA binding protein, nuclear receptor binding protein 2, etc.) were downregulated following co-stimulation of SCHAS and LPS. Discussions : It is thought that microarrays will play an ever-growing role in the advance of our understanding of the pharmacological actions of SCHAS in the treatment of arthritis. But further studies are required to concretely prove the effectiveness of SCHAS.