• Journal of Life Science
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• v.19 no.3
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• pp.362-365
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• 2009

Type 2 diabetes is a typical polygenic disease complex, for which several common risk alleles have been identified. The hepatocyte nuclear factor-$4{\alpha}$ (HNF-$4{\alpha}$), a transcription factor involved in the regulation of serum lipid and glucose levels, has recently been associated with type 2 diabetes. Therefore, we investigated the genotype for the C>T polymorphism at position 12352 of the HNF-$4{\alpha}$ gene in Koreans and compared patient genotypes with those of the control group. 100 patients (63 males, 37 females) with a history of type 2 diabetes (T2DM) and 100 controls (36 males, 64 females) participated in this study. There was no association between 12352 C>T polymorphism in the HNF-$4{\alpha}$ gene and T2DM. The present study shows that HNF-$4{\alpha}$ 12352 C>T polymorphism may not be associated with the pathogenesis of T2DM. Further studies with larger populations may be needed for the development of diagnostic methods at a genetic level such as DNA chip.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.96-106
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• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Korean Electrochemical Society
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• v.5 no.3
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• pp.125-130
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• 2002

An attempt was made for the application of porous reticular metal to a heat dissipation material in semiconductor process. For this aim, the electrodeposition of Fe/Ni alloy on the porous reticular Cu has been performed to minimize the thermal expansion mismatch between Cu skeleton and electronic chip. Preliminary tests for the electrodeposition of Fe/Ni alloy layer were conducted by using standard Hull Cell to examine the effect of current density on the composition of alloy layer. It seemed that mass transfer affected significantly the composition of Fe/Ni layer due to anomalous codeposition in the electrodeposition of Fe/Ni alloy. A paddle type stirring bath, which was employed to control the mass transfer of electrolyte in the work, was found to allow the electrodeposition Fe/Ni with a precise composition. result showed that the thermal expansion of Fe/Ni alloy layer was much lower than that of pure copper. From the tests of heat dissipation by using the apparatus designed in the work the heat dissipation material fabricated in the work showed the excellent heat dissipation capacity, namely, more than two times as compared to that of pure copper plate.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.7 no.3
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• pp.17-25
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• 2012

Wire bonding process in making semiconductor needs the most precise control and Critical To Quality(CTQ). Thus, it is regarded to be the most essential step in packaging process. In this process, pure gold wire is used to connect the chip and PCB(substrate or lead frame). However, the price of gold has been skyrocketing continuously for a long period of time and is expected to further increase in the near future. This phenomenon situates us in an unfavorable condition amidst the competitive environment. To avoid this situation, many semiconductor material making companies developed new types of wires: Au.Ag wire is one material followed by many others. This study is aimed to optimize the parameter in wire bonding with the use of 6sigma and QFD(Quality Function Deployment). 6sigma process is a good means to not only solve the problem, but to increase productivity. In order to find the key factor, we focused on VOB(Voice of Business) and VOC(Voice of Customer). The main factors from VOB, VOC are called CTQ. However, there were times when these main factors were far from offering us the correct answer, thus making the situation more difficult to handle. This study shows that QFD aids in deciding which of the accurate factors to undertake. Normally QFD is used in designing and developing products. 6sigma process is held more effective when it used with QFD.

• Journal of Life Science
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• v.19 no.10
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• pp.1495-1498
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• 2009

Type 2-diabetes is a typical polygenic disease complex, for which several common risk alleles have been identified. Adiponectin, which modulates insulin resistance as well as glucose and lipid metabolism, has recently been associated with type 2-diabetes (T2DM). Therefore, we investigated the genotype for the T45G and G267T polymorphisms in adiponectin genes in the Korean population and compared genotypes of patients with those of a control group. 100 patients (63 male, 37 female), who previously underwent T2DM and 100 controls (36 male, 63 female) participated in this study. There was a strong association between T45G polymorphism in the adiponectin gene and T2DM. The present study shows that adiponectin T45G polymorphism may be associated with the pathogenesis of T2DM. Further studies with a larger population may be needed for the development of diagnostic methods at genetic levels such as DNA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

• Science of Emotion and Sensibility
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• v.13 no.1
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• pp.235-242
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• 2010

Emotion science is one of the rapidly expanding engineering/scientific disciplines which has a major impact on human society. Such growing interests in emotion science and engineering owe the recent trend that various academic fields are being merged. In this paper we review the recent techniques in the measuring the emotion related elements and applications which include animal model system to investigate the neural network and behaviour, artificial nose/neuronal chip for in-depth understanding of sensing the outer stimuli, metabolic controlling using emotional stimulant such as sounds. In particular, microfabrication techniques made it possible to construct nano/micron scale sensing parts/chips to accommodate the olfactory cells and neuron cells and gave us a new opportunities to investigate the emotion precisely. Recent developments in the measurement techniques will be able to help combine the social sciences and natural sciences, and consequently expand the scope of studies.

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.881-891
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• 2020

Recently, the Ministry of Land, Infrastructure and Transport and the Ministry of Science and ICT are developing the Land Observation Satellite (CAS-500) to meet increased demand for high-resolution satellite images. Expected image products of CAS-500 includes precision orthoimage, Digital Surface Model (DSM), change detection map, etc. The quality of these products is determined based on the geometric accuracy of satellite images. Therefore, it is important to make precision geometric corrections of CAS-500 images to produce high-quality products. Geometric correction requires the Ground Control Point (GCP), which is usually extracted manually using orthoimages and digital map. This requires a lot of time to acquire GCPs. Therefore, it is necessary to automatically extract GCPs and reduce the time required for GCP extraction and orthoimage generation. To this end, the Precision Image Processing (PIP) System was developed for CAS-500 images to minimize user intervention in GCP extraction. This paper explains the products, processing steps and the function modules and Database of the PIP System. The performance of the System in terms of processing speed, is also presented. It is expected that through the developed System, precise orthoimages can be generated from all CAS-500 images over the Korean peninsula promptly. As future studies, we need to extend the System to handle automated orthoimage generation for overseas regions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.28-34
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• 2010

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA(Variable Gain Amplifier), filter, comparator to recovery the received signal. The proposed automatic reference voltage generator, positive peak detector, negative peak detector, and data slicer circuit can adjust the decision level of reference voltage over the received signal amplitudes. The transmitter is designed to drive high voltage and current to meet the 15693 specification. By using inductor loading circuit which can swing more than power supply and drive large current even under low impedance condition, it can control modulation rate from 30 percent to 5 percent, 100 perccnt and drive the output currents from 5 mA to 240 mA depending on standards. The 13.56 MHZ RFID reader is implemented in $0.18\;{\mu}m$ CM08 technology at 3.3V single supply. The chip area excluding pads is $1.5mm\;{\times}\;1.5mm$.