• Korean Journal of Agricultural and Forest Meteorology
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• v.19 no.4
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• pp.270-279
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• 2017

Regional assessment of crop productivity using a gridded simulation approach could aid policy making and crop management. Still, little effort has been made to develop the systems that allows gridded simulations of crop growth using ORYZA 2000 model, which has been used for predicting rice yield in Korea. The objectives of this study were to develop a series of data processing modules for creating input data files, running the crop model, and aggregating output files in a region of interest using gridded data files. These modules were implemented using C++ and R to make the best use of the features provided by these programming languages. In a case study, 13000 input files in a plain text format were prepared using daily gridded weather data that had spatial resolution of 1km and 12.5 km for the period of 2001-2010. Using the text files as inputs to ORYZA2000 model, crop yield simulations were performed for each grid cell using a scenario of crop management practices. After output files were created for grid cells that represent a paddy rice field in South Korea, each output file was aggregated into an output file in the netCDF format. It was found that the spatial pattern of crop yield was relatively similar to actual distribution of yields in Korea, although there were biases of crop yield depending on regions. It seemed that those differences resulted from uncertainties incurred in input data, e.g., transplanting date, cultivar in an area, as well as weather data. Our results indicated that a set of tools developed in this study would be useful for gridded simulation of different crop models. In the further study, it would be worthwhile to take into account compatibility to a modeling interface library for integrated simulation of an agricultural ecosystem.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• Proceedings of the Korean Society of Life Science Conference
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• 2001.06a
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• pp.67-86
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• 2001

A strain producing strongly fibrinolytic enzyme was isolated from soil and was identified to be Bacillus subtilis by biochemical and physiological characterization. The optimal culture conditions for the production of fibrinolytic enzyme was determined to be 1.0% tryptone, 1.5% soluble starch, 0.5% Peptone, 0.5% NaCl, $(NH_{4})_{3}PO_4.3H_{2}O, and MgSO_{4}.7H_{2}O.$ Initial pH and temperature were pH 8.0 and $30^{\circ}C$ , respectively, The highest enzyme production was observed at 30 hours of cultivation at $30^{\circ}C$ The fibrinolytic enzyme was purified to homogeneity by DEAE Sephadex A-50 ion exchange column chromatography, 70% ammonium sulfate precipitation, Sephadex G-200 and G-75 gel filtration column chromatography. The molecular weight of the purified enzyme was 28,000 as determined by sodium dodecyl sulfate-polyacrylamide gel electrophoresis. A gene encoding the fibrinolytic enzyme was cloned into a plasmid vector pBluescript, transforming E.coli XL-1 Blue. The clone was able to degrade fibrin, This indicated that the gene could encode a fibrinolytic enzyme. The nucleotide sequence of the 2.7 kb insert was determined in both direction. One open reading frame composed of 1023 nucleotides was found to be a potential protein coding region. There was the putative Shine-Dalgano sequence and TATA box upstream of the open reading frame. The homology search data in the genome database showed that both the 2.7 kb insert and 1 kb open reading frame carried no significance in the nucleotide sequence of known fibrinolytic enzyme from Bacillus serovars. The recombinant cell harboring the novel gene involved in fibrinolysis was subjected to protein purification. The molecular mass of the purified fibrinolytic enzyme was determined to be 31864 Dalton, which was highly in accordance with the molecular mass(33 kDa) of the fibrinolytic gene deduced from the insert. The fibrinolytic enzyme was Purified 50.5 folds to homogeneity in overall yield of 10.7% by DEAE Sephadex A-50 ion exchange, 85% ammonium sulfate precipitation, Sephadex G-50, Superdex 75 HR FPLC gel filtration. In conclusion, a novel fibrinolytic gene from Bacillus subtilis was identified and characterized by cloning a genomic library of Bacillus subtilis into pBleuscript. For the soybean fermented by this strain, it is found that there increased assistant protein about 20% compared to the soybean not fermented and increased about 30% according to amino acid analysis and, in particular, essential amino acid increased about 40%. When keeping this fermented soybean powder at room temperature for about 70days, it showed very high stability maintaining almost perfect activity and, therefore, it gave us great suggestion its possibility of development as a new functional food.

• Journal of Life Science
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• v.15 no.6 s.73
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• pp.851-856
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• 2005

Although valuable microbes have been isolated from the soil for the various productions of useful components, the microbes which can be cultivated in the laboratory are only $0.1-1\%$ of all microbes. To solve this problem, the study has recently been tried for making the valuable components from the environment by directly separating unculturable micrbial DNA in the soil. But it is known that humic acid originated from the soil interrupts various restriction enzymes and molecular biological process. Thus, in order to prevent these problems, this study modified the method separated soil DNA with phenol, CTAB and PEG. In order to compare the degree of purity for each DNA and the molecular biological application process, $A_{260}/A_{280}$ ratio, restriction enzymes, and PCR were performed. In case of DNA by the modified method, total yield of DNA was lower but $A_{260}/A_{280}$ ratio was higher than the previously reported methods. It was confirmed that the degree of purity is improved by the modified method. But it was not cut off by all kinds of tested restriction enzymes because of the operation of a very small amount of interrupting substances. When PCR was operated with each diluted DNA in different concentrations and GAPDH primer, the DNA by the modified method could be processed for PCR in the concentration of 100 times higher than by the previously reported separation method. Therefore, this experiment can find out the possibility of utilization for the unknown substances by effectively removing the harmful materials including humic acid and help establishing metagenomic DNA library from the soil DNA having the high degree of purity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.13-23
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• 2001

This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.81-93
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• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.21-34
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• 2002

In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.