• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.129.1-129.1
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• 2011

a-Si:H/c-Si 구조의 이종접합 태양전지 전면 투명전도막으로 Indium tin oxide(ITO) 박막의 조건에 따라 태양전지 특성을 연구하였다. ITO 박막은 파우더 타겟으로 마그네트론 스퍼터링 방식으로 성막하였고, 증착 온도(Ts)에 따라 전기적, 광학적 특성을 비교, 분석하였다. 기판 증착 온도가 증가할수록 박막의 저항이 낮아지는 것으로 나타났으며 $350^{\circ}C$ 조건에서 가장 낮은 저항($34.2{\Omega}$/sq)을 보였다. 투과도 또한 기판 증착 온도가 올라갈수록 전반적인 향상을 나타냈다. a-Si:H/c-Si 기판의 MCLT(minority carrier lifetime)는 $350^{\circ}C$에서 최적($359{\mu}s$)의 결과를 나타냈다. 그 이상의 기판 온도에서는 오히려 감소하였는데, 이는 높은 온도에서의 a-Si:H/c-Si 계면의 열손상으로 판단된다.

• Applied Science and Convergence Technology
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• 제24권1호
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• pp.22-26
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• 2015

The optical properties of InP/GaP short-period superlattice (SPS) structures grown at various temperatures from $400^{\circ}C$ to $490^{\circ}C$ have been investigated by using temperature-dependent photoluminescence (PL) and emission wavelength-dependent time-resolved PL measurements. The PL peak energy for SPS samples decreases as the growth temperature increases. The decreased PL energy of ~10 meV for the sample grown at $425^{\circ}C$ compared to that for $400^{\circ}C$-grown sample is due to the CuPt-B type ordering, while the SPS samples grown at $460^{\circ}C$ and $490^{\circ}C$ exhibit the significant reduction of the PL peak energies due to the combined effects of the formation of lateral composition modulation (LCM) and CuPt-B type ordering. The SPS samples with LCM structure show the enhanced carrier lifetime due to the spatial separation of carriers. This study represents that the bandgap energy of InP/GaP SPS structures can be controlled by varying growth temperature, leading to LCM formation and CuPt-B type ordering.

• Journal of Power Electronics
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• 제14권6호
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• pp.1109-1118
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• 2014

A Fundamental Frequency Sorting Algorithm (FFSA) is proposed in this paper to balance the voltages of floating dc capacitors for Modular Multilevel Converters (MMCs). The main idea is to change the sequences of the CPS-PWM carriers according to the capacitor voltage increments during the previous fundamental period. Excessive frequent sorting is avoided and many calculating resources are saved for the controller. As a result, more sub-modules can be dealt with. Furthermore, it does not need to measure the arm currents. Therefore, the communication between the controllers can be simplified and the number of current sensors can be reduced. Moreover, the proposed balancing method guarantees that all of the switching frequencies of the sub-modules are equal to each other. This is quite beneficial for the thermal design of the sub-modules and the lifetime of the power switches. Simulation and experimental results acquired from a 9-level prototype verify the viability of the proposed balancing method.

• 한국재료학회지
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• 제12권6호
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• pp.431-435
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• 2002

The dark current and photocurrent(PC) spectrum of Mg-doped GaN thin film were investigated with various bias voltages and temperatures. At high temperature and small bias, the dark current is dominated by holes thermally activated from an acceptor level Al located at about 0.16 eV above the valence band maximum $(E_v)$, The PC peak originates from the electron transition from deep level A2 located at about 0.34 eV above the $E_v$ to the conduction band minimum $(E_ C)$. However, at a large bias voltage, holes thermally activated from A2 to Al experience the field-in-duces tunneling to form one-dimensional defect band at Al, which determines the dark current. The PC peak associated with the transition from Al to $E_ C$ is also observed at large bias voltages owing to the extended recombination lifetime of holes by the tunneling. In the near infrared region, a strong PC peak at 1.20 eV appears due to the hole transition from deep donor/acceptor level to the valence band.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1361-1363
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• 1998

Poly-Si grain boundaries act as potential barriers as well as recombination centers for the photo-generated carriers in solar cells. Thereby, grain boundaries of poly-Si are considered as a major source of the poly-Si cell efficiency was reduced This paper investigated grain boundary effect of poly-Si wafer prior to the solar cell fabrication. By comparing I-V characteristics inner grain, on and across the grain boundary, we were able to detect grain potentials. To reduce grain boundary effect we carried out pretreatment, $POCl_3$ gettering, and examined carrier lifetime. This paper focuses on resistivity variation effect due to grain boundary of poly-Si. The resistivity of the inner grain was $2.2{\Omega}-cm$, on the grain boundary$2.3{\Omega}-cm$, across the grain boundary $2.6{\Omega}-cm$. A measured resistivity varied depending on how many grains were included inside the four point probes. The resistivity increased as the number of grain boundaries increased. Our result can contribute to achieve high conversion efficiency of poly-Si solar cell by overcoming the grain boundary influence.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• 신재생에너지
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• 제8권1호
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• pp.24-34
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• 2012

The main issue of boron doped p-type czochralski-grown silicon solar cells is the degradation when they are exposed to light or minority carriers injection. This is due to the meta-stable defect such as boron-oxygen in the Cz-Si material. Although a clear explanation is still researching, recent investigations have revealed that the Cz-Si defect is related with the boron and the oxygen concentration. They also revealed how these defects act a recombination centers in solar cells using density function theory (DFT) calculation. This paper reviews the physical understanding and gives an overview of the degradation models. Therefore, various methods for avoiding the light-induced degradation in Cz-Si solar cells are compared in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.158-166
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• 2001

Based on uniform hot carrier injection (optically assisted electron injection) across the $Si-SiO_2$ interface into the gate insulator of n-channel IGFETs, the threshold voltage shifts associated with electron injection of $1.25{\times}l0^{16}{\;}e/\textrm{cm}^2 between 0.5 and 7 MV/cm were found to decrease from positive to negative values, indicating both a decrease in trap cross section ($E_{ox}{\geq}1.5 MV/cm$) and the generation of FPC $E_{ox}{\geq}5{\;}MV/cm$). It was also found that FNC and large cross section NETs were generated for $E_{ox}{\geq}5{\;}MV/cm$. Continuous, uniform low-field (1MV/cm) electron injection up to $l0^{19}{\;}e/\textrm{cm}^2 is accompanied by a monatomic increase in threshold voltage. It was found that the data could be modeled more effectively by assuming that most of the threshold voltage shift could be ascribed to generated bulk defects which are generated and filled, or more likely, generated in a charged state. The injection method and conditions used in terms of injection fluence, injection density, and temperature, can have a dramatic impact on what is measured, and may have important implications on accelerated lifetime measurements.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.346.1-346.1
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• 2014

Porous nano crystalline $TiO_2$ is currently used as a working electrode in a dye-sensitized solar cell (DSSC). The conventional working electrode is comprised of absorption layer (particle size:~20 nm) and scattering layer (particle size:~300 nm). We inserted window layer with 10 nm particle size in order to increase transmittance and specific surface area of $TiO_2$. The electrochemical impedance spectroscope analysis was conducted to analysis characterization of the electronic behavior. The Bode phase plot and Nyquist plot were interpreted to confirm the internal resistance caused by the insertion of window layer and carrier lifetime. The photocurrent that occurred in working electrode, which is caused by rise in specific surface area, increased. Accordingly, it was found that insertion of window layer in the working electrode lead to not only effectively transmitting the light, but also increasing of specific surface area. Therefore, it was concluded that insertion of window layer contributes to high conversion efficiency of DSSCs.