• Title/Summary/Keyword: capacitor voltage

Search Result 1,824, Processing Time 0.025 seconds

A SOC Coefficient Factor Calibration Method to improve accuracy Of The Lithium Battery Equivalence Model (리튬 배터리 등가모델의 정확도 개선을 위한 SOC 계수 보정법)

  • Lee, Dae-Gun;Jung, Won-Jae;Jang, Jong-Eun;Park, Jun-Seok
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.54 no.4
    • /
    • pp.99-107
    • /
    • 2017
  • This paper proposes a battery model coefficient correction method for improving the accuracy of existing lithium battery equivalent models. BMS(battery management system) has been researched and developed to minimize shortening of battery life by keeping SOC(state of charge) and state of charge of lithium battery used in various industrial fields such as EV. However, the cell balancing operation based on the battery cell voltage can not follow the SOC change due to the internal resistance and the capacitor. Various battery equivalent models have been studied for estimation of battery SOC according to the internal resistance of the battery and capacitors. However, it is difficult to apply the same to all the batteries, and it tis difficult to estimate the battery state in the transient state. The existing battery electrical equivalent model study simulates charging and discharging dynamic characteristics of one kind of battery with error rate of 5~10% and it is not suitable to apply to actual battery having different electric characteristics. Therefore, this paper proposes a battery model coefficient correction algorithm that is suitable for real battery operating environments with different models and capacities, and can simulate dynamic characteristics with an error rate of less than 5%. To verify proposed battery model coefficient calibration method, a lithium battery of 3.7V rated voltage, 280 mAh, 1600 mAh capacity used, and a two stage RC tank model was used as an electrical equivalent model of a lithium battery. The battery charge/discharge test and model verification were performed using four C-rate of 0.25C, 0.5C, 0.75C, and 1C. The proposed battery model coefficient correction algorithm was applied to two battery models, The error rate of the discharge characteristics and the transient state characteristics is 2.13% at the maximum.

A 12b 200KHz 0.52mA $0.47mm^2$ Algorithmic A/D Converter for MEMS Applications (마이크로 전자 기계 시스템 응용을 위한 12비트 200KHz 0.52mA $0.47mm^2$ 알고리즈믹 A/D 변환기)

  • Kim, Young-Ju;Chae, Hee-Sung;Koo, Yong-Seo;Lim, Shin-Il;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.11 s.353
    • /
    • pp.48-57
    • /
    • 2006
  • This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

Preparation of $SrTiO_3$ Thin Film by RF Magnetron Sputtering and Its Dielectric Properties (RF 마그네트론 스퍼터링법에 의한 $SrTiO_3$박막제조와 유전특성)

  • Kim, Byeong-Gu;Son, Bong-Gyun;Choe, Seung-Cheol
    • Korean Journal of Materials Research
    • /
    • v.5 no.6
    • /
    • pp.754-762
    • /
    • 1995
  • Strontium titanate(SrTiO$_3$) thin film was prepared on Si substrates by RF magnetron sputtering for a high capacitance density required for the next generation of LSTs. The optimum deposition conditions for SrTiO$_3$thin film were investigated by controlling the deposition parameters. The crystallinity of films and the interface reactions between SrTO$_3$film and Si substrate were characterized by XRD and AES respectively. High quality films were obtained by using the mixed gas of Ar and $O_2$for sputtering. The films were deposited at various bias voltages to obtain the optimum conditions for a high quality file. The best crystallinity was obtained at film thickness of 300nm with the sputtering gas of Ar+20% $O_2$and the bias voltage of 100V. The barrier layer of Pt(100nm)/Ti(50nm) was very effective in avoiding the formation of SiO$_2$layer at the interface between SrTiO$_3$film and Si substrate. The capacitor with Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si structure was prepared to measure the electric and the dielectric properties. The highest capacitance and the lowest leakage current density were obtained by annealing at $600^{\circ}C$ for 2hrs. The typical specific capacitance was 6.4fF/$\textrm{cm}^2$, the relative dielectric constant was 217, and the leakage current density was about 2.0$\times$10$^{-8}$ A/$\textrm{cm}^2$ at the SrTiO$_3$film with the thickness of 300nm.

  • PDF

Improvement of Fluid Penetration Efficiency in Soil Using Plasma Blasting (플라즈마 발파를 이용한 토양 내 유체의 침투 효율 개선)

  • Baek, In-Joon;Jang, Hyun-Shic;Song, Jae-Yong;Lee, Geun-Chun;Jang, Bo-An
    • The Journal of Engineering Geology
    • /
    • v.31 no.3
    • /
    • pp.433-445
    • /
    • 2021
  • Plasma blasting by high voltage arc discharge were performed in laboratory-scale soil samples to investigate the fluid penetration efficiency. A plasma blasting device with a large-capacity capacitor and columnar soil samples with a diameter of 80 cm and a height of 60 cm were prepared. Columnar soil samples consist of seven A-samples mixed with sand and silt by ratio of 7:3 and three B-samples by ratio of 9:1. When fluid was injected into A-sample by pressure without plasma blasting, fluid penetrated into soil only near around the borehole, and penetration area ratio was less than 5%. Fluid was injected by plasma blasting with three different discharge energies of 1 kJ, 4 kJ and 9 kJ. When plasma blasting was performed once in the A-samples, penetration area ratios of the fluid were 16-25%. Penetration area ratios were 30-48% when blastings were executed five times consecutively. The largest penetration area by plasma blasting was 9.6 times larger than that by fluid injection by pressure. This indicates that the higher discharge energy of plasma blasting and the more numbers of blasting are, the larger are fluid penetration areas. When five consecutive plasma blasting were carried out in B-sample, fluid penetration area ratios were 33-59%. Penetration areas into B-samples were 1.1-1.4 times larger than those in A-samples when test conditions were the same, indicating that the higher permeability of soil is, the larger is fluid penetration area. The fluid penetration radius was calculated to figure out fluid penetration volume. When the fluid was injected by pressure, the penetration radius was 9 cm. Whereas, the penetration radius was 27-30 cm when blasting were performed 5 times with energy of 9 kJ. The radius increased up to 333% by plasma blasting. All these results indicate that cleaning agent penetrates further and remediation efficiency of contaminated soil will be improved if plasma blasting technology is applied to in situ cleaning of contaminated soil with low permeability.