• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.128-129
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• 2007

We fabricated seeded $SrBi_2Ta_2O_9$(SBT) thin films using seeding technique on the $LaZrO_x$ (LZO)/Si structure. To evaluate the ferroelectric properties of seeded SBT thin films, we investigated the crystalline phase, the surface morphology, the capacitance-voltage (C-V) curve and the current density-voltage (J-V) curve of seeded films and then compared with the physical and electrical properties of unseeded films. As the result of that, the characteristics of seeded and unseeded films have a slight difference. Therefore, the ferroelectric properties of seeded SBT thin films are not necessarily superior than unseeded films.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.56-61
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• 2015

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1313-1314
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• 2007

This paper presents organic thin-film transistors (OTFTs) with poly(3-hexylthiophene)(P3HT) semiconductor and several polymeric dielectric materials of poly(vinyl phenol)(PVP), poly(vinyl alcohol)(PVA), and polyimide(PI) by using soluble process. The fabricated OTFT's have inverted staggered structure using transmission line method(TLM) pattern. In order to evaluate the electrical characteristics of the OTFT, capacitance-voltage(C-V) and current-voltage(I-V) were measured. C-V graphs were measured at several frequencies of 100 Hz, 1 kHz, and 1 MHz and ID-VDS graphs according to $V_{GS}$. The current on/off ratio and threshold voltage with each of PVP, PVA, and PI based OTFTs were measured to $10^3$, and -0.36, -0.41, and -0.62 V. Also, the calculated mobility with each of PVP, PVA, and PI was 0.097, 0.095, and 0.028 $cm^{2}V^{-1}s^{-1}$, respectively. In the cases of PVP and PVA, the hole mobility of P3HT was in excellent agreement with the published value of 0.1 $cm^{2}V^{-1}s^{-1}$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.497-503
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• 2015

It is essential to acquire an accurate and simple technique for extracting the interface trap density ($D_{it}$) in order to characterize the normally-off gate-recessed AlGaN/GaN hetero field-effect transistors (HFETs) because they can undergo interface trap generation induced by the etch damage in each interfacial layer provoking the degradation of device performance as well as serious instability. Here, the frequency-dependent capacitance-voltage (C-V) method (FDCM) is proposed as a simple and fast technique for extracting $D_{it}$ and demonstrated in normally-off gate-recessed AlGaN/GaN HFETs. The FDCM is found to be not only simpler than the conductance method along with the same precision, but also much useful for a simple C-V model for AlGaN/GaN HFETs because it identifies frequency-independent and bias-dependent capacitance components.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.237-237
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• 2011

본 연구에서는 중성입자빔과 일반적인 ICP 플라즈마를 이용하여 성장시킨 SiON 박막의 물리적 특성 및 전기적 특성을 비교하여 분석하였다. 중성입자빔 및 ICP 플라즈마를 이용하여 기판 온도 400$^{\circ}C$ 조건에서 공정 시간에 따라 각각의 SiON 박막을 성장시켰으며 SiON 박막에 metal insulator semiconductor(MIS) 구조를 만들어 capacitance-voltage (C-V), current-voltage (I-V) 특성, 박막 두께 및 박막 내의 질소 분포 등을 비교 분석하였다. 기판 온도 400$^{\circ}C$ 조건에서 형성시킨 중성입자빔 및 플라즈마-SiON 박막의 두께는 6.0~10.0 nm, 굴절률 (n)은 1.5~1.8이며, 유전 상수는 4.2~5.0이다. 중성입자빔 SiON 박막의 절연파괴 전압은 약 14 MV/cm 이며, 플라즈마-SiON 박막의 절연파괴전압은 약 9~11 MV/cm 수준으로 중성입자빔-SiON 박막에 비하여 낮은 수준이다. 따라서 중성입자빔을 이용하여 400$^{\circ}C$에서 하전 입자에 의한 손상이 없는 양질의 SiON 박막을 형성시킬 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.147-148
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• 2006

Ge nanocrystals(NCs)-embedded MOS capacitors are charactenzed in this work using capacitance-voltage measurement. High-k dielectrics $HfO_2$ are employed for the gate material m the MOS capacitors, and the C-V curves obtained from $O_2-$ and $NH_3$-annealed $HfO_2$ films are analyzed.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• Journal of the Korean Vacuum Society
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• v.15 no.6
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• pp.587-593
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• 2006

The circuit of the EEFL system and the inverter has been analyzed into the resistance RL, the capacitance C of the EEFL-backlight system, and the inductance of transformer in the inverter. The lamp resistance and capacitance are deter-mined from the phase difference is between the lamp current and voltage and from the Q-V diagram, respectively. The single Lamp of EEFL for 32' LCD-BLU has the resistance of $66\;k\Omega$ and the capacitance of 21.61 pF. The resistance, which is connected by parallel in the 20-EEFLS BLU, is $3.3\;k\Omega$ and the capacitance is 402.1 pF. The matching frequency in the operation of lamp system is noted as $\omega_M=1/\sqrt{L_2C(1-k^2)}$, where $L_2$ is the inductance of secondary coil and k is the coupling coefficient between primary and secondary coil. The lamp current and voltage has maximum value at the matching frequency in the LCD BLU system. The results of analytic solutions are in good agreement with the experimental results.