• Title/Summary/Keyword: capacitance - voltage (C-V)

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Analysis of C-V Characteristics of MIS Structure Based on OTFT Technology for Flexible AM-OLED (Flexible AM-OLED를 위한 OTFT 기술 기반의 MIS 구조 C-V 특성 분석)

  • Kim, Jung-Seok;Kim, Byoung-Min;Chang, Jong-Hyeon;Ju, Byeong-Kwon;Pak, Jung-Ho
    • Proceedings of the KIEE Conference
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    • 2006.10a
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    • pp.77-78
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    • 2006
  • 최근 flexible OLED의 구동에 사용하기 위한 유기박막트랜지스터(Organic Thin Film Transistor, OTFT)의 연구에서는 용매에 용해되어 spin coating이 가능한 재료의 개발에 관심을 두고 있다. 현재 pentacene으로는 아직 spin coating으로 제작할 수 있는 상용화된 제품이 없고 spin coating이 가능한 활성층 물질(active material)로 P3HT가 쓰이고 있다. 본 연구에서는 용해 가능한 P3HT 활성층 물질과 여러 종류의 용해 가능한 게이트 절연물(gate insulator, Gl)을 사용하여 안정된 소자를 구현할 수 있는 공정을 개발하는 목적으로 metal-insulator-semironductor(MIS) 소자를 제작하여 C-V 특성을 측정하고 분석하였다. 먼저 7mm${\times}$7mm 크기의 pyrex glass 시편 위에 바닥 전극으로 $1600{\AA}$ Au을 증착하고 spin coating 방식을 이용하여 PVP, PVA, PVK, BCB, Pl의 5종류의 게이트 절연층을 각각 형성하였고 그 위에 같은 방법으로 P3HT를 코팅하였다. P3HT 코팅 시 bake 공정의 유무와 spin rpm의 변화에 따른 P3HT의 두께를 측정하였다. Gl의 종류별로 주파수에 따른 capatltancc를 측정하여 비교, 분석하였다. C-V 측정 결과 PVP, PVA, PVK, BCB, Pl의 단위 면적당 capacitance 값은 각각 1.06, 2.73, 2.94, 3.43, $2.78nF/cm^2$로 측정되었다. Threshold voltage, $V_{th}$는 각각 -0.4, -0.7, -1.6, -0.1, -0.2V를 나타냈다. 주파수에 따른 capacitance 변화율을 측정한 결과 Gl 물질 모두 주파수가 높을수록 capacitance가 점점 감소하는 경향을 보였으나 1${\sim}$2nF 이내의 범위에서 작은 변화율만 나타냈다. P3HT의 두께와 bake 온도를 변화시켜 C-V 값을 측정한 결과 차이는 없었다. FE-SEM으로 관찰한 결과에서도 두께나 온도에 따른 P3HT의 표면 morphology 차이를 확인할 수 없었다. 본 연구에서 PVK와 P3HT의 조합이 수율(yield)면에서 가장 안정적이면서 $3.43\;nF/cm^2$의 가장 높은 capacitance 값을 나타내고 $V_{th}$ 값 또한 -1.6V로 가장 낮은 값을 보였다.

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A Novel Structure for the Improved Switching Time of 50V Class Vertical Power MOSFET

  • Cho, Doohyung;Park, Kunsik;Kim, Kwangsoo
    • Journal of IKEEE
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    • v.19 no.1
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    • pp.110-117
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    • 2015
  • In this paper, a novel trench power MOSFET using a Separate-W-gated technique MOSFET (SWFET) is proposed. Because the SWFET has a very low $Q_{GD}$ compared to other forms of technology, it can be applied to high-speed power systems. The results found that the SWFET-applied $Q_{GD}$ was decreased by 40% when compared to simply using the more conventional trench gate MOSFET. $C_{ISS}$ (input capacitance : $C_{GS}+C_{GD}$), $C_{OSS}$ (output capacitance : $C_{GD}+C_{DS}$) and $C_{RSS}$ (reverse recovery capacitance : $C_{GD}$) were improved by 24%, 40%, and 50%, respectively. The switching characteristics of the inverter circuit shows a 24.9% enhancement of reverse recovery time, and the power efficiency of the DC-DC buck converter increased by 14.2%. In addition, the proposed SWFET does not require additional process steps and There was no degradation in the electrical performance of the current-voltage and on-resistance.

Fabrication and Electrical Properties of CuPc FET with Different Substrate Temperature (CuPc FET의 기판온도에 따른 제작 및 전기적 특성 연구)

  • Lee, Ho-Shik;Yang, Seong-Ho;Park, Yong-Pil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.06a
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    • pp.548-551
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    • 2007
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different substrate temperature. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET.

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Electrical Properties of CuPc-OFET with Metal Electrode (금속 전극에 따른 CuPc-OFET 의 전기적 특성)

  • Lee, Ho-Shik;Park, Yong-Pil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.751-753
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    • 2007
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm. and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

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Electrical Characteristics on MOS Structure with Irradiation of Radiation (방사선이 조사된 MOS구조에서의 전기적 특성)

  • 임규성;고석웅;정학기
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.10a
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    • pp.644-647
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    • 2001
  • The investigations were discussed on the radiation effects of the electrical properties to the p-type MOS capacitors, which were irradiated by cobalt-60 gamma ray sources. The characteristics of capacitance-bias voltage(C-V) and of dielectric dissipation tarter-bias voltage(D-V) on the capacitors were measured at 1 [MHz] frequency. The microscopic behaviors of spate charges in oxide and silicon-silicon dioxide(Si- $SiO_2$) interface were investigated from the experimental data. The C-V characteristics are statical and convenient for the evaluation of the steady state behavior of carriers and interface states characteristics. While, the distribution and magnitude of space charges in oxide can be found out accurately on the $V_{dp}$ in D-V curves. The density of interface states can be deduced with ease from the magnitude of D-peak at depletion state. Thus, it is also concluded that the D-V curves are more useful and easier than conventional C-V curves for analysis of the microscopic and dynamic behavior of carriers in oxide and Si- $SiO_2$interface.

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Development of Optimum Parameters Sampling Program for Mica Capacitor Design (마이카 커패시터 설계를 위한 최적 파라미터 추출 프로그램 개발)

  • Kim, Jae-Wook;Ryu, Chang-Keun
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.194-199
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    • 2009
  • In this study, ultra high-voltage (170kV AC), reliable 80pF mica capacitors for partial discharge system application were investigated. For capacitors design, Program was developed to sampling of series and parallel parameters. Mica was used as the dielectric of the capacitors. Using the conservative design rule, over 3 individual 50$\mu$m thick mica sheets with a size of 30mm$\times$35mm were used with lead foils to form a parallel capacitor element and 20 mica sheets were interleaved with lead foils to form a series stack of parallel capacitor element to meet the requirements of the capacitors. The dimension of the fabricated 80pF capacitor for 17kV AC were 90mm$\times$90mm. The high-frequency characteristics of the capacitance (C) and dissipation factor (D) of the developed capacitors were measured using a capacitance meter. The developed capacitor exhibited C of 79.5pF, had D of 0.001% over the frequency ranges of 150kHz to 50MHz, had a self-resonant frequency of 65MHz.

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Analysis of the Leakage Current in Poly Si TFTs (다결정 실리콘 박막트랜지스터의 누설전류 해석)

  • Lee, In-Chan;Ma, Tae-Young;kim, Sang-Hyun
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.801-802
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    • 1992
  • Poly Si TFTs have been fabricated from low temperature annealed a-Si films. I-V and C-V characteristics in the off-state region were measured. Analytical model for the leakage current in the off-state was suggested. In the measurement, capacitance increased abruptly with Increasing gate and drain voltage. This phenomena is attributed to the leakage current.

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Characteristics of $Pt/SrBi_2Ta_2O_9/ZrO_2/Si$ structures for NDRO ERAM (NDRO FRAM 소자를 위한 $Pt/SrBi_2Ta_2O_9/ZrO_2/Si$ 구조의 특성에 관한 연구)

  • 김은홍;최훈상;최인훈
    • Journal of the Korean Vacuum Society
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    • v.9 no.4
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    • pp.315-320
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    • 2000
  • We have investigated the crystal structure and electrical properties of Pt/SBT/$ZrO_2$/Si (MFIS) and Pt/SBT/Si (MFS) structures for the gate oxide of ferroelectric memory. XRD spectra and SEM showed that the SBT film of SBT/$ZrO_2$/Si structure had larger grain than that of SBT/Si structure. $ZrO_2$ film between SBT film and Si substrate is confirmed as a good candidate for a diffusion barrier by the analysis of AES. The remanent polarization decreased and coercive voltage increased in Pt/SBT/$ZrO_2$/Pt/$SiO_2$/Si structure. This effect may increase memory window of MFIS structure directly related to the coercive voltage. From the capacitance-volt-age characteristics, the memory windows of Pt/SBT (210 nm)/$ZrO_2$ (28 nm)/Si structure were in the range of 1~l.5 V at the applied voltage of 4~6 V. The current densities of Pt/SBT/ZrO$_2$/Si with as -deposited Pt electrode and annealed at $800^{\circ}C$ in $O_2$ambient were $8\times10^{-8} A/\textrm{cm}^2$ and $4\times10^{-8}A/\textrm{cm}^2$ , respectively.

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Electrical Characteristics of Oxide due to High Temperature Diffusion. (고온 확산공정에 따른 산화막의 전기적 특성)

  • Hong, N.P.;Choi, D.J.;Ko, K.Y.;Lee, T.S.;Choi, B.H.;Hong, J.W.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07a
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    • pp.63-66
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    • 2003
  • In this paper, the electrical characteristics of single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of poly backseat was researched. The oxide quality was examined through capacitance-voltage characteristics, and besides, it will be describe the capacitance-voltage characteristics of the single oxide layer by semiconductor device simulation.

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Inorganic ferroelectric materials for LC alignment for high performance display design

  • Lee, Won-Gyu;Choe, Ji-Hyeok;Na, Hyeon-Jae;Im, Ji-Hun;Han, Jeong-Min;Hwang, Jeong-Yeon;Seo, Dae-Sik
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.11a
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    • pp.161-161
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    • 2009
  • Ion bombarded inorganic materials for LC alignment has been researched as it provides controllability in a nonstop process for producing high-resolution displays. Many optically transparent insulators such as $SiOx$ and a-C:H have been investigated as potential candidates for inorganic alignment materials. Even so, LC orientation on a new material with superior capacity is required to produce high-performance displays. Many inorganic materials with high permittivities can reduce the voltage losses due to the LC alignment layer that are a trade-off for its capacitance. The minimum voltage for device operation can be applied to the LC under low external voltage using these materials. This means that low power consumption for LCD applications can be achieved using a high-k alignment structure in which the LC can be driven effectively with a low threshold voltage. Among the many other potential high-k oxides, HfO2 is considered to be one of the most promising due to its remarkable properties of high dielectric constant, relatively low leakage current, large band gap (5.68 eV), and high transparency. Due to these characteristics, HfO2 can be used in LC alignment to increase the capacitance of the inorganic alignment layer for low-voltage driving of LCs.

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