• Journal of the Semiconductor & Display Technology
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• 제20권4호
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• Journal of Computing Science and Engineering
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• 제11권2호
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• pp.69-77
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• 2017

Recent GPUs have adopted cache memory to benefit general-purpose GPU (GPGPU) programs. However, unlike CPU programs, GPGPU programs typically have considerably less temporal/spatial locality. Moreover, the L1 data cache is used by many threads that access a data size typically considerably larger than the L1 cache, making it critical to bypass L1 data cache intelligently to enhance GPU cache performance. In this paper, we examine GPU cache access behavior and propose a simple hardware-based GPU cache bypassing method that can be applied to GPU applications without recompiling programs. Moreover, we introduce a hybrid method that integrates static profiling information and hardware-based bypassing to further enhance performance. Our experimental results reveal that hardware-based cache bypassing can boost performance for most benchmarks, and the hybrid method can achieve performance comparable to state-of-the-art compiler-based bypassing with considerably less profiling cost.

• Journal of Korea Society of Industrial Information Systems
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• 제18권5호
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• pp.67-72
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• 2013

A low-power bypassing Booth multiplier for mobile multimedia applications is proposed. The bypassing structure directly transfers input values to outputs without switching the internal nodes of a multiplier, enabling low-power design. The proposed Booth multiplier adopts the bypassing structure while the bypassing is usually adopted in the Braun multipliers. Simulation results show the proposed Booth multiplier achieves an 11% reduction in terms of the proposed FoM compared to prior works.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.70-70
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• 2010

Until recently. the study about bypass diode has been limited to theoretical study. but, in this paper, We study on the relationship between structure of PV module and Bypassing point by simulation software(Pspice). We expected the design on the PV module has an effect on bypassing point. So, we designated the two kind of experiment with PV modules. One of the experiment is on the relationship between the number of rows and Bypassing point on the PV modules, the other experiment is on the relationship between the number of groups(two columns) on the PV modules.(around 50Wp, 100Wp, 150Wp, 200WP) As the result, the more increase the number of rows, bypassing point is faster. And the more increase the number of groups in more than 3 groups, bypassing point is faster more than case of increasing the rows.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제59권12호
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• pp.2212-2217
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• 2010

Previous studies have been focused on the voltage of Bypass diode and Isc(Short Circuit Current) of the influenced solar cell. The Bypass diode starts working when it gets the reverse applied voltage. Previous studies have only concentrated on Isc of the influenced solar cell and Imp of PV module to explain the bypassing performance. PV module is usually working together with inverter having MPPT(Maximum Power Point Tracking) function for best performance. bypassing point is regulated by MPPT function of inverter. In this paper, simulation results of Bypass diode in PV module have been analyzed to represent the relationship of the bypassing point with the composition of PV module. From the results, the more cells are connected with each string, the earlier bypassing performance happens under the fixed number of strings. As diode groups increase or irradiation decreases, the bypassing performance starts fast.

• Journal of Information Processing Systems
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• 제17권1호
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• pp.51-62
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• 2021

On-chip caches of graphics processing units (GPUs) have contributed to improved GPU performance by reducing long memory access latency. However, cache efficiency remains low despite the facts that recent GPUs have considerably mitigated the bottleneck problem of L1 data cache. Although the cache miss rate is a reasonable metric for cache efficiency, it is not necessarily proportional to GPU performance. In this study, we introduce a second key determinant to overcome the problem of predicting the performance gains from L1 data cache based on the assumption that miss rate only is not accurate. The proposed technique estimates the benefits of the cache by measuring the balance between cache efficiency and throughput. The throughput of the cache is predicted based on the warp occupancy information in the warp pool. Then, the warp occupancy is used for a second bypass phase when workloads show an ambiguous miss rate. In our proposed architecture, the L1 data cache is turned off for a long period when the warp occupancy is not high. Our two-level bypassing technique can be applied to recent GPU models and improves the performance by 6% on average compared to the architecture without bypassing. Moreover, it outperforms the conventional bottleneck-based bypassing techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.150-153
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• 2015

An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.976-978
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• 1998

In this paper, we designed basic concept and structure of bypassing device which promoted the activity of low voltage line-fuse, when it perceived the too small short-fault current to activate line-fuse which located at the between secondary of pole transformer and home immediately. And we study displacement of bypass contact and electromagnetic force caused by the short-fault current by the basic experiment to understand the basic characteristic of bypassing movements.

• Journal of The Korean Society of Agricultural Engineers
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• 제58권6호
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• pp.9-21
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• 2016

Agricultural reservoirs in Korea have been recognized as an emerging resource for recreational and cultural activities for residents. However, most of the reservoirs are eutrophic and showing high level of contamination with nuisance algal bloom and offensive odor during the summer. For better management and restoration of the reservoirs' water quality, scientific modeling approaches could be used to diagnose the problems and evaluate the efficacy of alternative control measures. The objectives of this study were to validate the performance of a three-dimensional (3D) hydrodynamic and water quality model (Environmental Fluid Dynamics Code, EFDC) for a eutrophic agricultural reservoir and assess the effect of bypassing of the effluent from a wastewater treatment plant on the reservoir water quality. The 3D model successfully simulated the temporal variations of water temperature, DO, TOC, nitrogen and phosphorus species and Chl-a observed in 2014 and also captured their spatial heterogeneity in the reservoir. The simulation results indicated that the point source bypassing may reduce the T-N and T-P concentrations of the reservoir by 6.6 ~ 8.2 %, and 1.7 ~ 16.8 %, respectively. The bypassing, however, showed a marginal effect on the control of TOC due to the increased algal biomass associated with the increased water retention time after bypassing as well as the lower TOC level of the effluent compared to the ambient reservoir water.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅲ
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• pp.1383-1386
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• 2003

In this paper, an ALU for Simultaneous Multi-Threading (SMT) microprocessors is designed. The SMT architecture improves notably performance and utilization of processes compared with conventional superscalar architectures by executing instructions from multiple threads at the same time. This ALU adopts data bypassing method to process multi-threads. And it can flush instructions in the same thread that generate exceptions such as branch misprediction. interrupt etc, performance of SMT microprocessors with data bypassing and exception handler can be improved.