• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.37-41
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• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.799-806
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• 2000

Cu$_{6}$Sn$_{5}$-dispersed 63Sn-37Pb solder bumps of 760$\mu\textrm{m}$ size were fabricated on Au(0.5$\mu\textrm{m}$)/Ni(5$\mu\textrm{m}$)/Cu(27$\pm$20$\mu\textrm{m}$) BGA substrates by screen printing process, and their shear strength were characterized with variations of dwell time at reflow peak temperature and aging time at 15$0^{\circ}C$ . With dwell time of 30 seconds at reflow peak temperature, the solder bumps with Cu$_{6}$Sn$_{5}$ dispersion exhibited higher shear strength than the value of the 63Sn-37Pb solder bump. With increasing the dwell time longer than 60 seconds, however the shear strength of the Cu$_{6}$Sn$_{5}$-dispersed solder bumps became lower than that the 63Sn-37Pb solder bumps. The failure surface of the solder bumps could be divided into two legions of slow crack propagation and critical crack propagation. The shear strength of the solder bumps was inversely proportional to the slow crack propagation length, regardless of the dwell time at peak temperature, aging time at 150 $^{\circ}C$ and the volume fraction of Cu$_{6}$Sn$_{5}$ dispersion.> 5/ dispersion.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.351-357
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• 2005

Comparison of shear strength and shear energy of the 48Sn-52In solder bumps reflowed on Cu UBM were made with variations of reflow temperature from $150^{\circ}C$ to $250^{\circ}C$ and reflow time from 1 min to 20 min to establish an evaluation method for the mechanical reliability of solder bumps. Compared to the shear strength, the shear energy of the Sn-52In solder bumps was much more consistent with the solder reaction behavior and the fracture mode at the Sn-52In/Cu interface, indicating that the bump shear energy can be used as an effective tool to evaluate the mechanical integrity of solder/UBM interface.

• Journal of the Korean institute of surface engineering
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• v.36 no.5
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.9
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• pp.471-475
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• 2001

ln this paper, a micromachined micromechanical switch is presented. The presented switch is operated in the vertical direction to the substrate by an electrostatic force between two parallel plates. The moving plate is pulled down to connect the bumps of the bias node$(V_{DD}/ or GND)$ to the bumps of the output node when a oltage difference exists between the moving plate and the input plate. The switch was designed to operate at a low switching voltage$(\risingdotseq5V)$ by including a large-area, narrow-gap, parallel plate capacitor A theoretical analysis of the designed switch was performed in order to determine its geometry fitting the desired pull-in voltage and release voltage. The designed switch was fabricated by surface micromachining combined with Ni electroplating. From the experimental results of the fabricated switch, its pull-in voltage came Out to be less than 5V and the measured maximum allowable current was 150mA. The measured average ON-state resistance was about 8$\Omega$, and the OFF-state resistance was too high to be measured with digital multimeter.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.73-78
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• 2016

An increase in the transistor density of integrated circuit devices leads to a very high increase in heat dissipation density, which causes a long-term reliability and various thermal problems in microelectronics. In this study, liquid cooling method was investigated using straight microchannels with various metal bumps. Microchannels were fabricated on Si wafer using deep reactive ion etching (DRIE), and Ag, Cu, or Cr/Au/Cu metal bumps were placed on Si wafer by a screen printing method. The surface temperature of liquid cooling structures with various metal bumps was measured by infrared (IR) microscopy. For liquid cooling with Cr/Au/Cu bumps, the surface temperature difference before and after liquid cooling was $45.2^{\circ}C$ and the power density drop was $2.8W/cm^2$ at $200^{\circ}C$ heating temperature.

• Journal of IKEEE
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• v.16 no.2
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• pp.102-108
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• 2012

3-dimensional integrated circuits (3D-ICs) have some problems for power delivery network design due to larger supply currents and larger power delivery paths compared to 2D-IC. The power delivery network consists of power bumps & through-silicon-vias (TSVs), and IR-drop at each node varies with the number and location of power bumps & TSVs. It is important to optimize the power bumps & TSVs while IR-drop constraint is satisfied in order to operate chip ordinarily. In this paper, the power bumps & TSVs optimization with optimized power mesh structure for power delivery network in 3D-ICs is proposed.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.1-10
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• 2023

Recently, as the demand for high-performance computers and mobile products increases, semiconductor packages are becoming high-integration and high-density. Therefore, in order to transmit a large amount of data at once, micro bumps such as flip-chip and Cu pillar that can reduce bump size and pitch and increase I/O density are used. However, when the size of the bumps is smaller than 70 ㎛, the brittleness increases and electrical properties decrease due to the rapid increase of the IMC volume fraction in the solder joint, which deteriorates the reliability of the solder joint. Therefore, in order to improve these issues, a layer that serves to prevent diffusion is inserted between the UBM (Under Bump Metallization) or pillar and the solder cap. In this review paper, various studies to improve bonding properties by suppressing excessive IMC growth of micro-bumps through additional layer insertion were compared and analyzed.

• Tribology and Lubricants
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• v.19 no.2
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• pp.102-108
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• 2003

The height of laser bumps has been considered as the limit of the minimum flying height in the contact start-stop (CSS) of hard disk drives. In this paper, tribological interactions at flying height under laser bumps are investigated in a spin stand for development of ultra-low flying head-disk interface. With the reduction of the spinning speed in a spin stand, the flying height is decreased under the height of laser bumps and, then, head-disk interactions are investigated using AE and stiction/friction signals. During seek tests and 20000 cycle-sweep tests, AE and stiction/friction signals are not significantly changed and there are no catastrophic failures of head-disk interface. Bearing analysis and AFM analysis show that there are signs of wear and plastic deformation on the disks. It is suggested that flying height could be as low as and, sometimes, lower than laser bump height.