• The KIPS Transactions:PartC
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• v.9C no.1
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• pp.73-78
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• 2002

In WATM networks, in order to perform dynamic slot allocation required slots of mobile terminals are estimated based on DP (Dynamic Parameter) reflecting characteristics of traffic. In VBR (Variable Bit Rate) traffic, slot allocation is done at MT considering both time-dependent characteristics and QoS (Quality of Service) requirements. In this paper, DPs-buffer state information and buffer state change-are transmitted through in-band signaling. BS (Base Station) performs dynamic slot allocation considering traffic characteristics of each MT (Mobile Terminal), in other words, buffer state information informs the potentiality of 'buffer full state'to BS if MT buffer is over the specific threshold value and buffer state change notifies change in buffer state of incoming cells to MT. If buffer state information is equal to 'low (more than threshold)' and 'abrupt increase' it generates 'buffer full' state cell transmission delay or cell loss might occur. At this time BS should assign additional slots to MT, and then MT consumes cells in its buffer. In simulation, the proposed scheme shows better performance in cell delay and loss than EPSA (Estimation-Prorated Slot Assignment) in-band scheme.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.11
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• pp.5343-5364
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• 2016

Considering the tradeoff between energy consumption and outage behavior in buffer-aided relay selection, a novel energy-efficient buffer-aided optimal relay selection scheme with power adaptation and Inter-Relay Interference (IRI) cancellation is proposed. In the proposed scheme, energy consumption minimization is the objective with the consideration of relay buffer state, outage probability and relay power control, in order to eliminate IRI. The proposed scheme selects a pair of optimal relays from multiple candidate relays, denoted as optimal receive relay and optimal transmit relay respectively. Source-relay and relay-destination communications can be performed within a time-slot, which performs as Full-Duplex (FD) relaying. Markov chain model is applied to analyze the evolution of relay buffer states. System steady state outage probability and achievable diversity order are derived respectively. In addition, packet transmission delay and power reduction performance are investigated with a specific analysis. Numerical results show that the proposed scheme outperforms other relay selection schemes in terms of outage behavior with power adaptation and IRI cancellation in the same relay number and buffer size scenario. Compared with Buffer State relay selection method, the proposed scheme reduces transmission delay significantly with the same amount of relays. Average transmit power reduction can be implemented to relays with the increasing of relay number and buffer size, which realizes the tradeoff between energy-efficiency, outage behavior and delay performance in green cooperative communications.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.4
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• pp.1579-1602
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• 2020

In the design of production system, buffer capacity allocation is a major step. Through polymorphism analysis of production capacity and production capability, this paper investigates a buffer allocation optimization problem aiming at the multi-stage production line including unreliable machines, which is concerned with maximizing the system theoretical production rate and minimizing the system state entropy for a certain amount of buffers simultaneously. Stochastic process analysis is employed to establish Markov models for repairable modular machines. Considering the complex structure, an improved vector UGF (Universal Generating Function) technique and composition operators are introduced to construct the system model. Then the measures to assess the system's multi-state reliability and structural complexity are given. Based on system theoretical production rate and system state entropy, mathematical model for buffer capacity optimization is built and optimized by a specific genetic algorithm. The feasibility and effectiveness of the proposed method is verified by an application of an engine head production line.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.04a
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• pp.435-444
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• 1995

We propose a new approach to the calculation of the exact cells loss probability in a shared buffer ATM multiplexer, which is loaded with homogeneous discrete-time ON-OFF sources. Renewal cycles are identified in regard to the state of input sources and the buffer state on each renewal circle is modelled as a K(shared buffer size)-state Markov chain. We also analyze the behavior of queue build-up at the shared buffer whose distribution together with the steady-state probabilities of the Markov chain leads to the exact cell loss probability. Our approach to obtaining the exact cell loss probability seems to be more efficient than most of other existing ones since our underlying Markov chain has less number of states.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.442-460
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• 2001

In video-on-demand(VOD) systems it is important to minimize initial latency and memory requirements. The minimization of initial latency enables the system to provide services with short response time, and the minimization of memory requirements enables the system to service more concurrent user requests with the same amount of memory. In VOD systems, since initial latency and memory requirement increase according to the increment of buffer size allocated to user requests, the buffer size allocated to user requests must be minimized. The existing static buffer allocation scheme, however, determines the buffer size based on the assumption that thy system is in fully loaded state. Thus, when the system is in partially loaded state, the scheme allocates user requests unnecessarily large buffers. This paper proposes a dynamics buffer allocation scheme that allocates user requests the minimum buffer size in fully loaded state as well as a partially loaded state. This scheme dynamically determines the buffer size based on the number of user requests in service and the number of user requests arriving while servicing current requests. In addition, through analyses and simulations, this paper validates that the dynamics buffer allocation outperforms the statics buffer allocation in initial latency and the number of concurrent user requests that can be supported. Our simulation results show that, in proportion to the static buffer allocation scheme, the dynamic buffer allocation scheme reduces the average initial latency by 29%~65%, and in a systems having several disks. increases the average number of concurrent user requests by 48%~68%. Our results show that the dynamic buffer allocation scheme significantly improves the performance and reduce the capacity requirements of VOD systems.

• Journal of IKEEE
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• v.22 no.2
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• pp.402-407
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• 2018

Link selection strategy has been an important technical issues of relay network. In this paper, we introduce a link selection scheme in the bidirectional, buffer-aided relay network. Three kinds of information such as the states of the queue at the relay buffer, the qualities of the links, and the states of the queues at the user buffer are considered. Throughput and delay performance is evaluated under three cases with different available information.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.677-684
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• 2003

Most policies of VOD services are mainly studied about server system, and make no touch on clients buffer stabilization which is the basis of guaranteeing playback quality and playing without cut off. In this paper, we proposed a skipping frame transfer policy that can sending dynamic buffer control signal to server in accordance with clients buffer state of starvation or overrun, and server transfers a skipped frame to client after receive the control signal. And through a simulation, we show the suggested policy is more efficiency on playback quality by buffer stabilization which is by preventing loss and miss for receiving frame due to grow worse client buffer state.

• Journal of applied mathematics & informatics
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• v.33 no.1_2
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• pp.185-191
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• 2015

This paper considers a discrete-time buffer system with session-based arrivals, an infinite storage capacity and one unreliable output line. There are multiple different types of sessions and the output line is governed by a finite state Markov chain. Based on a generating functions approach, we obtain an exact expression for the mean buffer content.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.215-222
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• 2013

NAND flash memory-based Solid State Drives (SSD) have lots of merits compared to traditional hard disk drives (HDD). However, random write in SSD is still far slower than sequential read/write and random read. There are two independent approaches to resolve this problem: 1) using part of the flash memory blocks as log blocks, and 2) using internal write buffer (DRAM or Non-Volatile RAM) in SSD. While log blocks are managed by the Flash Translation Layer (FTL), write buffer management has been treated separately from FTL. Write buffer management schemes did not use the exact status of log blocks and log block management schemes in FTL did not consider the behavior of write buffer management scheme. In this paper, we first show that log blocks and write buffer have a tight relationship to each other, which necessitates integrated management of both of them. Since log blocks also can be viewed as another type of write buffer, we can manage both of them as an integrated write buffer. Then we provide three design criteria for the integrated write buffer management scheme which can be very useful to SSD firmware designers.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.140-145
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• 2002

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).