• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.9
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• pp.417-422
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• 2002

ZnO thin films were deposited on various substrates, such as Si-(111), SiO$_2$(5000 $\AA$ by thermal CVD)/Si-(100), and SiO$_2$(2000 $\AA$ by RF sputtering)/Si-(100). The (002)-orientation, surface morphology and roughness, and electrical resistivity of deposited films were measured and compared in terms of substrate. Surface acoustic wave(SAW) filters with a multilayered configuration of IDT/ZnO/SiO$_2$/Si were also fabricated and the IDT was obtained using a lift-off method. From the frequency-response characteristics of fabricated devices, the insertion loss and side-lobe rejection were estimated. The experimental results showed that the (002)-oriented growth nature of ZnO films, which played a crucial role of determining the characteristic of SAW device, was strong1y dependent upon the SiO$_2$buffer.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.9
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• pp.198-203
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• 2019

An adhesive wireless bookbinding machine was designed with optimal motor control and automatic cover insertion for bookbinding. The noise level was improved by modifying the thrust of the machine and changing from a compressor method to an AC induction motor control method. The automatic cover insertion function was added to improve the task speed. Motor and decelerator damage can be caused by sudden braking and acceleration of the motor rotation (clockwise and counter-clockwise), so a buffer-type locational control system was developed to secure stable movement and durability. The complicated internal design was also simplified, and the volume and weight were decreased. The results show that the noise was decreased by 57% from 135 dB to 71.7 dB, and the task speed was decreased by 57% from 18 s to 9.58 s. The automatic cover insertion was designed to supply a maximum of 130 sheets per supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.235-235
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• 2009

This paper describes the influence of a polycrystalline (poly) 3C-SiC buffer layer on the surface acoustic wave (SAW) properties of poly aluminum nitride (AlN) thin films by comparing the center frequency, insertion loss, the electromechanical coupling coefficient ($k^2$), andthetemperaturecoefficientoffrequency(TCF) of an IDT/AlN/3C-SiC structure with those of an IDT/AlN/Si structure, The poly-AlN thin films with an (0002)-preferred orientation were deposited on a silicon (Si) substrate using a pulsed reactive magnetron sputtering system. Results show that the insertion loss (21.92 dB) and TCF (-18 ppm/$^{\circ}C$) of the IDT/AlN/3C-SiC structure were improved by a closely matched coefficient of thermal expansion (CTE) and small lattice mismatch (1 %) between the AlN and 3C-SiC. However, a drawback is that the $k^2(0.79%)$ and SAW velocity(5020m/s) of the AlN/3C-SiC SAW device were reduced by appearing in some non-(0002)AlN planes such as the (10 $\bar{1}$ 2) and (10 $\bar{1}$ 3) AlN planes in the AlN/SiC film. Although disadvantages were shown to exist, the use of the AlN/3C-SiC structure for SAW applications at high temperatures is possible. The characteristics of the AlN thin films were also evaluated using FT-IR spectra, XRD, and AFM images.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• Korean Journal Plant Pathology
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• v.10 no.1
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• pp.39-46
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• 1994

Pseudomonas fluorescens Biovar III strains S-2 antagonistic to Rhizoctonia solani was subjected to Tn5 mutagenesis by the transposon vector pGS9. Ampicillin and kanamycin resistant (Ampr, Kmr) transconjugants were recovered at a frequency of 1.3$\times$10-7 per initial recipient cell, when recipient cells were washed twice in TE buffer before conjugation. Of the ca. 3000 transconjugants, a frequency of noninhibitory (Inh-), nonfluorescent (Flu-) and auxotorphic (Pro-) mutants were 0.27%, 0.47% and 0.40%, respectively. In these mutants, all Inh- mutants showed the same colony morphology as wild type, whereas all Flu- and Pro- mutants inhibited the growth of R. solani. These mutants were also susceptible to chloramphenicol, indicating only the Tn5 element, except for parts of pGS9, was integrated into the recipient genome. In a Southern blot analysis, the Tn5 element inserted into one site on the chromosome for each of the chosen mutants. However, Tn5 insertion sites of Inh-, and Pro- mutants were differed in each other. These indicate that the genes essential for R. solani inhibition, fluorescent production and auxotrophic are chromosomally located, but not linked to each other.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.641-652
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• 2002

We introduce a new ultra-large capacity time- and wavelength-division hybrid optical switching system, called ESCIMONET(Easily SCalable Interconnected Multiwavelength Optical NETwork). We describe its architecture, principle of operation, and performance characteristics. ESCIMONET is very effective system in terms of its handling capacity versus number of wavelength needed. It can handle n$^3$number of channels using only n number of different wavelengths. The insertion loss of the whole system is less than conventional optical switching system so that the number of optical amplifiers in the system can be minimized. We analyzed the performance of the system by investigation the characteristics of the buffer used in the system such as throughput and average waiting time of the signal in a buffer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.782-787
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• 2000

The monolithic single-pole three-throw(SP3T) GaAs PIN diode switch circuit for the broadband and high power application was designed, fabricated and characterized. To improve the power handling capability, buffer layers of the diode employ both low temperature buffer and superlattice buffer. The diode show the breakdown voltage of 65V and turn-on voltage of 1.3V. The monolithic integrated switch employed microstrip lines and backside via holes for low-inductance signal grounding. The vertical epitaxial PIN structure demonstrated better microwave performance than planar type structures due to lower parasitics and higher quality intrinsic region. As the large signal characteristics of the fabricated SP3T MMIC switch, the insertion loss was measured less than 0.6dB and the isolation better than 50dB when the input power was increased from 8dBM to 32dBm at 14.5GHz.

• Korean Journal of Metals and Materials
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• v.49 no.10
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• pp.811-817
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• 2011

In this study, we have investigated the role of a metal oxide hole injection layer (HIL) between an Indium Tin Oxide (ITO) electrode and an organic hole transporting layer (HTL) in organic light emitting diodes (OLEDs). Nickel Oxide films were deposited at different deposition times of 0 to 60 seconds, thus leading to a thickness from 0 to 15 nm on ITO/glass substrates. To study the influence of NiO film thickness on the properties of OLEDs, the relationships between NiO/ITO morphology and surface properties have been studied by UV-visible spectroscopy measurements and AFM microscopy. The dependences of the I-V-L properties on the thickness of the NiO layers were examined. Comparing these with devices without an NiO buffer layer, turn-on voltage and luminance have been obviously improved by using the NiO buffer layer with a thickness smaller than 10 nm in OLEDs. Moreover, the efficiency of the device ITO/NiO (< 5 nm)/NPB/$Alq_3$/ LiF/Al has increased two times at the same operation voltage (8V). Insertion of a thin NiO layer between the ITO and HTL enhances the hole injection, which can increase the device efficiency and decrease the turn-on voltage, while also decreasing the interface roughness.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.159-162
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• 2002

The eleventh-order coupled line lowpass filter(LPF) was designed to suppress harmonics and spurious signals. The microstrip type LPF was fabricated using a high-$T_{c}$ superconductor(HTS) $YBa_{2}$$Cu_{3}$$O_{7-x}$(YBCO) thin film with the $CeO_{2}$ buffer layer which was deposited on the sapphire ($Al_{2}O_{3}$) substrate of 30 x 30 $mm^{2}$. The coupled-line type LPF was designed for 1.2 GHz of cutoff frequency with 0.01 dB of ripple level at passband. The fabricated HTS LPF shows excellent attenuation characteristics in stopband of 1.2~9.5GHz (7-attenuation poles in the stopband), and shows low insertion loss (0.2 dB) and return loss (17.1 dB) in the pass- band. These measured results match well with those obtained by the EM simulation. This clearly demonstrates that the HTS LPF can suppress harmonics and spurious signals effectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.