• The Transactions of the Korea Information Processing Society
• /
• v.5 no.4
• /
• pp.1025-1032
• /
• 1998

In this paper, the PLD design tool which realizes a digital circuit as PLD, by using EDIF netlist of the digital circuit designed at OrCAD have been developed. This paper is proposed the following algorithms: JIE(Joined Information Extractor) which extracts the connecting information between both cells in order to realize the digital circuit as PLD using the EDIF netlist, FND(Feedback Node Detector) which look into whether feedback exists or not, BEG(Boolean Equation Generator) which generates a boolean equation, and so on. Also, this paper is developed auto-select function which selects the PLD element with consideration of number of I/O variables of the minimized boolean equation, and algorithm generation JEDEC file of GAL6001 and GAL6002, having a forms of EPLD which is bigger than PLD.

• Korean Journal of Optics and Photonics
• /
• v.14 no.2
• /
• pp.166-168
• /
• 2003

By using gain saturation of semiconductor optical amplifiers (SOAs), an all-optical AND gate at 10 Gb/s has been successfully demonstrated. Firstly, Boolean (equation omitted) has been obtained using the first SOA with signal B and clock injection. Then, the all-optical AND gate is achieved using the second SOA with signals A and (equation omitted) injection.

• The Transactions of the Korea Information Processing Society
• /
• v.1 no.3
• /
• pp.391-397
• /
• 1994

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16R4, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.1
• /
• pp.25-34
• /
• 1981

Any logical stuckft faults in multivalued combinational circuits are analyzed using the concept of Boolean difference. The algebra employed is the implementation oriented algebra developed by Allen and Givone. All the lines in the circuit are classified into five types according to their properties. For each type, the equation that represents the complete test set is derived and proved. All the results in examples are confumed to be correct by comparing the truth tables of the normal and faulty circuits.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
• /
• 2004.10a
• /
• pp.382-387
• /
• 2004

As the increasing needs in the industrial filed, many studies for the 3D CAD system are carried out. There are two types of 3D CAD system. One is manifold modeler, the other is non-manifold modeler. In the manifold modeler only 3D objects can be modeled. In the non-manifold modeler 3D, 2D, 1D, and 0D objects can be modeled in a unified data structure. Recently there are many studies on the non-manifold modeler. Most of them are focused on finding unknown topological entities and representing all kinds of topological entities found. In this paper, efficient data structure is selected. The boundary information on a face and an edge is included in this data structure. The boundary information on a vertex is excluded considering the frequency of usage. Because the disk cycle information is not required in most case of modeling. It is compact. It stores essential non-manifold information such as loop cycle and radial cycle. A suitable Euler-Poincare equation is studied and selected. Using the efficient data structure and the selected Euler-Poincare equation, 18 basic Euler operators are implemented. Several 3D models are created using the implemented modeler. A non-manifold modeling can be carried out using the implemented 3D CAD system. The results of this paper could be used in the further studies such as an implementation of Boolean operators, and a translation of 2D CAD drawings to 3D models.

• Journal of Institute of Control, Robotics and Systems
• /
• v.7 no.11
• /
• pp.939-943
• /
• 2001

PLC(programmable Logic Controller)s essential components of modern automation systems encompassing almost every industry. Ladder Diagrams (LD) have been widely used in the design of such PLC since the LD is suitable for the modeling of the sequential control system. However, the synthesis of LD itself mainly depends on the experience of the industrial engineer, which may results in unstructured or inflexible design. Hence, in this paper, we propose a ladder diagram conversion algorithm which systematically produces LDs for PLCs based on discrete event models to enhance the structured and flexible design mechanism.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.12
• /
• pp.2181-2186
• /
• 2006

In this paper, a RTL binding technique for CPLD constraint is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in used CLB.

• Journal of Applied Reliability
• /
• v.6 no.2
• /
• pp.187-194
• /
• 2006

In this paper, We presented the algorithm for estimating a reliability between nodes in wireless communication network such as RBN and MANET To estimate the reliability between nodes, we first modeled RNB and MANET as probability graph. Branches of the graph are always reliable and the probability of node failure is independent. After all possible simple path which can be established between two nodes are examined, we perform sharp arithmetic to remove repetition event between two nodes. Using probability for each variable of the minimized Boolean equation, we present the reliability formula.

• Journal of Applied Reliability
• /
• v.6 no.4
• /
• pp.297-306
• /
• 2006

In this paper, We presented the algorithm for estimating a reliability between nodes in wireless distributed sensor networks (DSN). To estimate the reliability between nodes, we first modeled DSN as probability graph. Links of the graph are always reliable and the probability of node failure is independent. After all possible simple path which can be established between two nodes are examined, we perform sharp operation to remove repetition event between two nodes. Using probability for each variable of the minimized Boolean equation, we present the reliability formula.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.2 s.40
• /
• pp.1-6
• /
• 2006

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.