• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.872-877
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• 2011

In this paper, the new decoding algorithm of Block Turbo Codes using Channel State Information(CSI), which is estimated to compensate for the distorted signal caused by multi-path fading, is proposed in order to improve error correction capacity during decoding procedure in OFDM system. The performance of the new decoding algorithm is compared to that of the conventional decoding algorithm without using channel state information under the Rayleigh fading channel. Experimental results showed that in case of only one iteration coding gains of up to 5.0dB~9.0dB can be obtained by applying the channel state information to the conventional decoding algorithm according to the modulation methods. In addition to that, the new decoding algorithm using channel state information at only one iteration shows a performance improvement of 3.5dB to 5.0dB when compared to the conventional decoding algorithm after four iterations. This leads to reduce the considerable amount of computation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.195-202
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• 2007

A differential space-frequency block code - orthogonal frequency division multiplexing (SFBC-OFDM) scheme as a multiple-input multiple-output (MIMO) transmission technique for next-generation digital multimedia broadcasting (DMB) is proposed in this paper. A linear decoding method for differential SFBC, which performs comparably to the ML decoding method, is derived for the cases of two or four transmit antennas. A simple table lookup method is proposed to improve the efficiency of the encoding/decoding process of DSFBC for the case of non-constant modulus constellations. A DMB MIMO channel model, developed by extending the 3GPP MIMO model to fit DMB environments, is used to compare BER performances of differential space block code schemes for various channel environments. Simulation results show that the differential SFBC-16QAM scheme using either four transmit antennas with one receive antenna or two transmit antennas with two receive antennas achieves a performance gain of 12dB than that of the conventional DQPSK scheme, even with a data rate twice faster.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Journal of Information Processing Systems
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• v.10 no.1
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• pp.69-80
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• 2014

The free distance of (n, k, l) convolutional codes has some connection with the memory length, which depends on not only l but also on k. To efficiently obtain a large memory length, we have constructed a new class of (2k, k, l) convolutional codes by (2k, k) block codes and (2, 1, l) convolutional codes, and its encoder and generation function are also given in this paper. With the help of some matrix modules, we designed a single structure Viterbi decoder with a parallel capability, obtained a unified and efficient decoding model for (2k, k, l) convolutional codes, and then give a description of the decoding process in detail. By observing the survivor path memory in a matrix viewer, and testing the role of the max module, we implemented a simulation with (2k, k, l) convolutional codes. The results show that many of them are better than conventional (2, 1, l) convolutional codes.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.75-80
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• 2004

An iterative soft-decision decoding algorithm of block codes is proposed. With careful examinations of the first hard-decision decoding result, the candidate codewords are efficiently searched for. An approach to reducing decoding complexity and lowering error probability is to select a small number of candidate codewords. With high probability, we include the codewords which are at the short distance from the received signal. The decoder then computes the distance to each of the candidate codewords and selects the codeword which is the closest. We can search for the candidate codewords which make the error patterns contain the bits with small reliability values. Also, we can reduce the cases that we select the same candidate codeword already searched for. Computer simulation results are presented for (23,12) Golay code. They show that decoding complexity is considerably reduced and the block error probability is lowered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.3
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• pp.336-341
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• 2014

When using a higher-order modulation scheme, there are variations in bit-reliability depending on the bit position in a modulation symbol. Variations of bit-reliability in the codeword block lower the decoding performance. Also, the decoding performance increases as the sum of the bit-reliabilities in the codeword block increases. This paper presents a novel hybrid automatic repeat request scheme that increases the sum of the reliabilities of the transmitted bits by lowering the modulation order, and decreases the variations of bit-reliability in the codeword block by preferentially retransmitting bits with low reliability. The proposed scheme outperforms the constellation rearrangement scheme. Furthermore, the proposed scheme also provides a good solution in cases where the size of the retransmission block is smaller than the size of the initial transmission block.

• ETRI Journal
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• v.28 no.5
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• pp.672-675
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• 2006

The effect of block interleaving in a low density parity check (LDPC)-turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed-Solomon (RS) code. Thus, an LDPC-turbo concatenated code can show better performance than the conventional RS-turbo concatenated code. Furthermore, the performance of an LDPC-turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.657-660
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• 2011

Differential detection algorithm for DBO-CSS based on maximum signal energy detection (MSED) using viterbi algorithm is proposed. In order to mitigate SNR degradation caused by differential decoding, a modified viterbi algorithm with so called correlation metric (CM) in every state is proposed. It is shown that the performance gain of the proposed algorithm when compared with that of the conventional differential detection with the block decoding algorithm is about 2.5dB at BER = $10^{-5}$.