• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.406-411
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• 2000

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1862-1867
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• 1999

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• ETRI Journal
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• v.34 no.1
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• pp.35-43
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• 2012

This paper presents a delay-locked-loop-based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a '01' clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-${\mu}m$ CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6B
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• pp.569-578
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• 2002

This paper proposes a new multicarrier code division multiple access (CDMA) system. The proposed multicarrier CDMA system provides the advantages that the transmission bandwidth is more efficiently utilized by using divided spreading sequence, time and frequency diversity is achieved in frequency selective nultipath (acting channel, and inter-carrier interference (ICI) can be minimized by using specific data and code pattern. In this system, transmitted data bits are serial-to-parallel converted to some parallel branches. On each branch each bit is direct-sequence spread-spectrum modulated by divided spreading sequences and transmitted using orthogonal carriers. The receiver providers a Rake for each carrier, and the outputs of Rakes are combined to get time and frequency diversity. This multicarrier CDMA system allows additional flexibility in the choice of system parameters. Upon varying system parameters, bit error rate (BER) performance is examined for the proposed multicarrier CDMA system. Simulation results show that the proposed multicarrier CDMA scheme can achieve better performance than the other types of conventional multicarrier CDMA systems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.278-285
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• 2011

This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

• Journal of Communications and Networks
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• v.7 no.1
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• pp.13-20
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• 2005

In this paper, a new multi carrier, direct sequence code division multiple access (MC-DS-CDMA) system is proposed. Our new signal construction is based on convolutional encoding of the transmitted data, serial-to-parallel (S/P) conversion of the encoded data, Walsh-Hadamard-transformation (WHT), a second S/P conversion of the WHT outputs, spread spectrum (SS) modulation with a common pseudo-noise (PN) sequence, and then multicarrier transmission. The system bit error rate (BER) performance in frequency selective fading channel in the presence of additive white Gaussian noise (AWGN) and a jamming tone is analyzed and simulated. The numerical results are compared with those from an orthogonal MC-DS-CDMA system of Sourour and Nakagawa [7]. It is shown that the two systems have almost the same BER performance, but the proposed scheme has better anti-jamming ability.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.