• ETRI Journal
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• v.35 no.3
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• pp.378-385
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• 2013

An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

• Journal of IKEEE
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• v.24 no.3
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• pp.895-900
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• 2020

In this paper, BSPE replaced the existing multiplication algorithm that consumes a lot of power. Hardware resources are reduced by using a bit-serial multiplier, and variable integer data is used to reduce memory usage. In addition, MOA resource usage and power usage were reduced by applying LOA (Lower-part OR Approximation) to MOA (Multi Operand Adder) used to add partial sums. Therefore, compared to the existing MBS (Multiplication by Barrel Shifter), hardware resource reduction of 44% and power consumption of 42% were reduced. Also, we propose a hardware architecture design for BSPE Core.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• ETRI Journal
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• v.32 no.4
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• pp.493-502
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• 2010

The operation time of an encoder is one of the critical implementation issues for satisfying the timing requirements of Long Term Evolution (LTE) systems because the encoder is based on binary operations. In this paper, we propose a design and implementation of a latency efficient encoder for LTE systems. By virtue of 8-bit parallel processing of the cyclic redundancy checking attachment, code block (CB) segmentation, and a parallel processor, we are able to construct engines for turbo codings and rate matchings of each CB in a parallel fashion. Experimental results illustrate that although the total area and clock period of the proposed scheme are 19% and 6% larger than those of a conventional method based on a serial scheme, respectively, our parallel structure decreases the latency by about 32% to 65% compared with a serial structure. In particular, our approach is more latency efficient when the encoder processes a number of CBs. In addition, we apply the proposed scheme to a real system based on LTE, so that the timing requirement for ACK/NACK transmission is met by employing the encoder based on the parallel structure.

• Journal of Broadcast Engineering
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• v.24 no.3
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• pp.485-494
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• 2019

A software-driven real-time frequency de-modulator is implemented with the aid of universal-serial-bus (USB) type software defined radio dongle. An analog stereo frequency modulation (FM) broadcast signal is down-converted to the basedband analog signal then converted to digital bit streams in the USB dongle. Computer software such as Matlab, Python, and GNU Radio manipulates the incoming bit streams with the technique of digital signal processing. Low pass filtering, band pass filtering, decimation, frequency discriminator, double sideband amplitude demodulation, phase locked loop, and deemphasis function blocks are implemented using such computer languages. Especially, GNU Radion is employed to realize the real-time demodulator.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.2
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• pp.193-199
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• 2017

In this paper, we proposed an architecture of error detection in $Z_N$ operations using $Z_{(2^r-1)N}$. The error detection can be simply constructed in hardware. The hardware overheads are only 50% and 1% with respectively space and time complexity. The architecture is very efficient because it is detection 99% for 1 bit fault. For 2 bit fault, it is detection 99% and 50% with respective r=2 and r=3.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.837-842
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• 2010

In this paper, quantum cryptography systems used in the design process inevitably open bit stream of pseudo-random number that exists multiple open channels between them and the need to share information on the part of the situation exposes a pair of bit stream. In this paper, the base test of pseudo-random number I tested out this process and the merge bit binary column look out for randomness.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.841-842
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• 2006

This paper has proposed a serial 8-bit DAC for column driver circuits of mobile displays using LTPS TFTs. The DAC circuit takes very small area by using parasitic capacitance of column lines as sampling and holding capacitors. Moreover, the proposed DAC does not need the analog buffer, because the DAC operation is performed on the column lines. For the data driver circuits of 2-inch qVGA OLED panel, the DAC area is $84um{\times}800um$ and the simulated DAC power consumption is 8.5mW with 10-V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.3
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• pp.171-183
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• 2018

Herein, we show the design and fabrication of a serial-to-parallel converter (SPC) using the $0.25-{\mu}m$ GaAs pHEMT process. The serial-to-parallel converter is composed of four bits to control the four phase shifters used in the core chip. The SPC stores the received serial data signal to a register in the SPC and converts the stored data into the parallel data. Each converted output data can control four phase shifters. The size of the fabricated SPC is $1,200{\times}480{\mu}m^2$ and it uses two DC power supplies of 5 V and -3 V. The consumption current of each DC power supply is 7.1 mA for 5 V, and 2.1 mA for -3 V.