1 |
N.S. Chang, T.H Kim, C.H. Kim, D.G. Han and H.W. Kim, "Efficient Finite Field Arithmetic Architectures for Pairing Based Cryptosystems," JKIISC, vol. 18, no. 3, pp. 33-43, June. 2008
|
2 |
R.Lidl and H. Niederreiter, "Introduction to finite fields and their applications," Cambridge University Press, Revised Edition, 1994
|
3 |
Nat'l Inst. of Standard and Technology, "Digital Signature Standard," FIPS Publication 182-2, Jan. 2000
|
4 |
IEEE Std. 1363-2000, "IEEE Standard Specification for Public-key Cryptography," Jan. 2000
|
5 |
M. Joye and M. Tunstall, "Fault Analysis in Cryptography," Springer, 2012
|
6 |
D.F. Barbe, "Very Large Scale Integration(VLSI)," New York, Springer-verlag, 1982
|
7 |
N.R Strader and V.T. Rhyne, "A canonical bit-sequential multiplier," IEEE Trans. Comput., Aug. 1982
|
8 |
T. J. Brosnan and N.R. Strader II, "Modular Error Detection for Bit-Serial Multiplication," IEEE Trans. Comput., vol. 37, no. 9, Sep. 1988
|
9 |
G. Zervakis, N. Eftaxiopoulos, K. Tso-umanis, N. Axelos and K. Pekmestzi, "A High Radix Montgomery Multiplier with Concurrent Error Detection," 9th International Design and Test Symposium, 2014
|
10 |
I. Duursma and H.S. Lee, "Tate pairing implementation for hyper elliptic curves ." Asiacrypt 2003, LNCS 2894, pp. 111-123, Springer-Verlag, 2003
|
11 |
R. Granger, D. Page, and M. Stam, "Hardware and software normal basis arithmetic for pairing based crypto-graphy in characteristic three," IEEE Transactions on Computers, vol. 54, no. 7, pp. 852-860, July. 2005
DOI
|
12 |
C.H. Kim, "Efficient Mod 3 Adder for Error Detction," Journal of Institute of Industrial Technology, 23, Semyung University, 2016
|
13 |
D. Page and N. Smart, "Hardware Implementation of Finite Fields of Characteristic Three," CHES 2002, LNCS 2523, pp. 529-539, Springer-Verlag, 2003
|
14 |
C.H. Kim and J-J. Quisqater, "Fault attacks for CRT based RSA : New attacks, New results, and New countermeasures," WiSTP 2007, LNCS 4462, pp. 215-228, 2007
|
15 |
D.N. Amanor, "Efficient Hardware Architectures for Modular Multi-plication," A Thesis of Degree of Master of Science, The University of Applied Science Offenburg, Germany, 2005
|
16 |
J-P. Deschamps, J.L. Imana and G. D. Sutter, "Harhware Implementation of Finite-Field Arithmetic," McGraw Hill, 2009
|
17 |
A. Miyamoto, N. Homma, T. Aoki, and A. Satoh, "Systematic design of RSA processor based on hig-hradix Montgomery Multipliers," IEEE Trans. VLSI Syst. vol. 19, no. 7, pp. 1136-1146, 2011
DOI
|