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http://dx.doi.org/10.13089/JKIISC.2017.27.2.193

Error Detection Architecture for Modular Operations  

Kim, Chang Han (Semyung University)
Chang, Nam Su (Sejong Cyber University)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.27, no.2, 2017 , pp. 193-199 More about this Journal
Abstract
In this paper, we proposed an architecture of error detection in $Z_N$ operations using $Z_{(2^r-1)N}$. The error detection can be simply constructed in hardware. The hardware overheads are only 50% and 1% with respectively space and time complexity. The architecture is very efficient because it is detection 99% for 1 bit fault. For 2 bit fault, it is detection 99% and 50% with respective r=2 and r=3.
Keywords
Modular Operation; Error Detection; Bit-Serial Multiplier;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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