• ETRI Journal
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• v.32 no.4
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.494-498
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• 1990

• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.7
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• pp.651-662
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• 1991

An improved modular multiplication algorithm for RSA type public key cryptosystem and its application to a serial communication cricuit are presented. Correction on a published fast modular multiplication algorithm is proposed and verified thru simulation. Cryptosystem for RS 232C communication protocol isdesigned and prototyped for low speed data exchange between computers. The system adops the correct algoroithm and operates successfully using a small size key.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1861-1871
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• 1994

This paper presents efficient real time software implementation methods for the grayscale morphological composite function processing (FP) system. The proposed method is based on a matrix representation of the composite FP system using a basis matrix composed of structuring elements. We propose a procedure to derive the basis matrix for composite FP systems with any grayscale structuring element (GSE). It is shown that composite FP operations including morphological opening and closing are more efficiently accomplished by a local matrix operation with the basis matrix rather than cascade operations, eliminating delays and requiring less memory storage. In the second part of this paper, a VLSI implementation architecture for grayscale morphological operators is presented. The proposed implementation architecture employs a bit-serial approach which allows grayscale morphological operations to be decomposed into bit-level binary operation unit for the p-bit grayscale singnal. It is shown that this realization is simple and modular structure and thus is suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1623-1632
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• 2004

In this paper, we analyze the performance of linear search and bit reversal search algorithms based on the single-dwell serial search for rapid UWB (Ultra Wide Band) signal acquisition in typical indoor wireless channel environments. Simulation results according to bin spacing and frame interval in IEEE 802.15 Task Group 3a UWB indoor wireless channels show that bit reversal search algorithm achieves much smaller normalized mean acquisition time than linear search algorithm. In particular, it is found that the normalized mean acquisition time of the bit reversal search according to the range of searching termination interval closely matches the ideal case. In addition, we observe that the acquisition performance of bit reversal search algorithm becomes much better as bin spacing gets finer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.336-344
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• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.406-411
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• 2000

In wireless ATM system, powerful FEC code is required for highly reliable data transmission. In this paper, we propose an adaptive hybrid ARQ scheme using RCPSCCC for WATM system. The code rate of RCPSCC is adjusted to match channel conditions and data types. By using only the effective free distances of outer and inner encoders, we derive upper bounds of the bit and word error probabilities over Rayleigh and Rician fading channels. By applying RCPSCC to the adaptive hybrid ARQ protocol, highly reliable data transmission can be achieved.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.