• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.406-409
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• 1997

An economical 4-axis CNC controller employing step motors is designed and implemented in this paper. By using the inherent ability of holding position of the motor, the CNC controller uses open-loop control for removing trajectory error and for a simple hardware. Each drive of axis has an 8-bit microprocessor 89C52 and a PC controls the axes and pendant by means of RS232C serial communication. Backlash is also compensated at the axis controller. While compensating the backlash, the feed rate becomes zero in order to minimize trajectory error. The trajectories of 16ms interval are computed on PC and are sent to motor drives. In the drives, the trajectories are linearly interpolated for 2ms interval. The developed CNC does not require add-on specific motion card on PC. From the experimental results, the validity of the CNC controller based on step motor is proved.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.165-168
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• 1998

제안하고 있는 CSD17C00 chip은 C&S technology에서 개발한 것으로, 음성 신호 처리를 위해 범용으로 구현되었으며, 16 bit 40 MIPS DSP group OAK DSP Core를 포함, 이에 Miscellaneous Logic, Serial Port, Host Interface, Timer, Compander 의 5가지 Peripherals 과 범용 I/O Ports 로 설계되었다. 1차적으로 CSD17C00 Chip 의 성능을 점검하였다. 그 결과, 응용 프로그램은 28MIPS의 계산속도를 갖으며, 프로그램 ROM 크기는 8.85KWords 이고, 10KWords 의 데이터 ROM 과 4KWords 데이터 RAM을 필요로 한다. CSD17C00 CHIP은 멀티미디어 통신용 VOCODER 개발을 위한 범용성을 갖추고 있으며, VOCODER 용 S/W 개발 환경 및 H/W 구조가 여타 범용 DSP에 비해편의성고 K합리성을 제공하도록 설계되어 있다. 따라서, 이를 이용한다면, 멀티 미디어 통신용 VOCODER, INTERNET PHONE CO-PROCESSOR, DIGITAL RECODER, MPEG AUDIO ENCODER & DECODER 등 다양한 제품으로의 응용이 가능할 것으로 전망된다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.3
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• pp.5-11
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• 1970

Some of the coding method have been discussed by extracting characteristics from vowels and consonants of Korean characters. given letters were sampled through 3$\times$5 mesh and also constituted first matrix system which taken subpatterns of vertical Conponent as variables and then, characteristics of the letters are extracted from the second matrix system expresses by common characteristics which are combined-with first one. Single coding was obtained by scanning the characteristic pattern. a good agree between theoretical values and their measurements and the reproducing of all vowels and consonants of Korean chasacters about coding were certified on the display designed.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1823-1824
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• 2008

We propose a remote controlled robot manipulator using force feedback joystick. User can control easily 5 d.o.f robot manipulator in 3 demensional space using general joystick. A force sensor attached in developed gripper sends signal to main robot controller so as to know gripper grasp the object. The signal also sent to user through force feedback joystick. We designed a dexterous 5 d.o.f robot manipulator analysis the kinematics and inverse kinematics. The robot was simply developed using serial RC motor. As a main robot controller, we use 32bit MPU(AT91SAM7256) and micro C/OS. To show the validity of our developed robot, a several experiments were demonstrated.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.571-573
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• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• 전기의세계
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• v.36 no.3
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• pp.190-204
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• 1987

본고에서는 이중입출력 메모리(Dual-Port RAM)를 이용한 영상 입력장치(Image Memory)의 설계 및 그 제어 신호 발생기에 대하여 논하였다. 이중 입출력 메모리 소자인 TMS4161은 기존의 표준 64K x 1DRAM Port와 256bit의 내부적 Shift REgister와 연결된 Serial Port가 있어서, 실시간 영상 처리 및 그래픽 용으로 사용하기에 적합하나, 그 사용에 있어서 가장 어려운 문제로 제안된 주소 신호 발생기 및 요구중재기에 대한 해결 방안을 제시하였다. 또한 서로 독립적인 두개의 입출력 장치가 있다는 장점을 이용하여 하드웨어에 의한 실시간 처리도 가능한 구조로 쉽게 확장할 수 있어서 소프트웨어에 의한 실시간 처리로 가능하리라 사료된다. 앞으로는 512x512x8의 영상 메모리 구조 뿐만 아니라 1024x1024x8의 영상메모리 구조에 대하여 더욱 연구할 필요가 있다고 본다.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2067-2070
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• 2002

In this paper, a VLSI architecture for transform and quantization module, which consists of 2D-DCT, quantization, AC/DC prediction block, scan conversion, inverse quantization and 2D-IDCT, is presented. The architecture of the module is designed to handle a macroblock data within 1064 cycles and suitable for MPEG-4 video codec handling CIF image formats. Only single 1-D DCT/IDCT cores are used for the design instead of 2-D DCT/IDCT, respectively. 1-bit serial distributed arithmetic architecture is adopted for 1-D DCT/IDCT to reduce the hardware area in this architecture. As the result, the maximum utilization of hardware can be achieved, and power consumption can be minimized. The proposed design is operated on 27MHz clock. The experimental results show that the accuracy of DCT and IDCT meet the IEEE specification.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.527-528
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• 2006

In this paper, we propose an IP design and implementation of System on a chip(SoC) for Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) processor using adder-based DA(Adder-based Distributed Arithmetic). To reduced hardware cost and to improve operating speed, the combined DCT/ DWT processor used the bit-serial method and DA module. The transform of coefficient equation result in reduction in hardware cost and has a regularity in implementation. We use Verilog-HDL and Xilinx ISE for simulation and implement FPGA on SoCMaster-3.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.10
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• pp.799-806
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• 1991

Utilizing dual basis, normal basis, and subfield representation, three different finite field multipliers are presented in this paper. First, we propose an extended dual basis multiplier based on Berlekamp's bit-serial multiplication algorithm. Second, a detailed explanation and design of the Massey-Omura multiplier based on a normal basis representation is described. Third, the multiplication algorithm over GF(($2^{n}$) utilizing subfield is proposed. Especially, three different multipliers are designed over the finite field GF(($2^{4}$) and the complexity of each multiplier is compared with that of others. As a result of comparison, we recognize that the extendd dual basis multiplier requires the smallest number of gates, whereas the subfield multiplier, due to its regularity, simplicity, and modularlity, is easier to implement than the others with respect to higher($m{\ge}8$) order and m/2 subfield order.