• Journal of IKEEE
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• v.23 no.4
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• pp.1321-1327
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• 2019

This paper describes an efficient hardware implementation of modular square root (MSQR) computation over GF(p), which is the operation needed to map plaintext messages to points on elliptic curves for elliptic curve (EC)-ElGamal public-key encryption. Our method supports five sizes of elliptic curves over GF(p) defined by the National Institute of Standards and Technology (NIST) standard. For the Koblitz curves and the pseudorandom curves with 192-bit, 256-bit, 384-bit and 521-bit, the Euler's Criterion based on the characteristic of the modulo values was applied. For the elliptic curves with 224-bit, the Tonelli-Shanks algorithm was simplified and applied to compute MSQR. The proposed method was implemented using the finite field arithmetic circuit with 32-bit datapath and memory block of elliptic curve cryptography (ECC) processor, and its hardware operation was verified by implementing it on the Virtex-5 field programmable gate array (FPGA) device. When the implemented circuit operates with a 50 MHz clock, the computation of MSQR takes about 18 ms for 224-bit pseudorandom curves and about 4 ms for 256-bit Koblitz curves.

• Journal of the Korea Computer Industry Society
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• v.10 no.3
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• pp.105-114
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• 2009

In this paper a modified Feistel network 128 bit block cipher algorithm is proposed. The proposed algorithm has a 128, 196 or 256 bit key and it updates a selected 32 bit word from input value whole by deformed Feistel Network structure. Existing of such structural special quality is getting into block cipher algorithms and big distinction. The proposed block cipher algorithm shows much improved software speed compared with international standard block cipher algorithm AES and domestic standard block cipher algorithm SEED and ARIA. It may be utilized much in same field coming smart card that must perform in limited environment if use these special quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1092-1097
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• 2011

An anti-collision protocol which tries to minimize the collision probability and identification time is the most important factor in all identification technologies. This paper focuses on methods to improve the efficiency of tag's process in identification systems. Our scheme, Binary Slotted Query Tree (BSQT) algorithm, is a memoryless protocol that identifies an object's ID more efficiently by removing the unnecessary prefixes of the traditional Query Tree (QT) algorithm. With enhanced QT algorithm, the reader will broadcast 1 bit and wait the response from the tags but the difference in this scheme is the reader will listen in 2 slots (slot 1 is for 0 bit Tags and slot 2 is for 1 bit Tags). Base on the responses the reader will decide next broadcasted bit. This will help for the reader to remove some unnecessary broadcasted bits which no tags will response. Numerical and simulation results show that the proposed scheme decreases the tag identification time by reducing the overall number of request.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.7
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• pp.3080-3099
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• 2016

In this paper, we propose an algorithm for energy efficient cooperative communication in wireless sensor network (WSN). The algorithm computes the appropriate transmission distance corresponding to optimal broadcast bit error probability, while taking the circuit energy consumption and the number of cooperating nodes into consideration. The algorithm guarantees minimum energy consumption by choosing higher value of bit error probability for cooperative phase and lower value of bit error probability for broadcast phase while maintaining the required end-to-end reliability. The simulation results show that the proposed algorithm provides significant energy saving gain when compared with traditional fixed distance schemes and is suitable for applications demanding energy efficiency with high quality of reception.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.6
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• pp.1149-1156
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• 2021

The Grover algorithm, which accelerates the brute force attack, is applicable to key recovery of symmetric key cryptography, and NIST uses the Grover attack cost for symmetric key cryptography to estimate the post-quantum security strength. In this paper, we estimate the attack cost of Grover's algorithm by implementing DES as a quantum circuit. NIST estimates the post-quantum security strength based on the attack cost of AES for symmetric key cryptography using 128, 192, and 256-bit keys. The estimated attack cost for DES can be analyzed to see how resistant DES is to attacks from quantum computers. Currently, since there is no post-quantum security index for symmetric key ciphers using 64-bit keys, the Grover attack cost for DES using 64-bit keys estimated in this paper can be used as a standard. ProjectQ, a quantum programming tool, was used to analyze the suitability and attack cost of the quantum circuit implementation of the proposed DES.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.609-612
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• 1999

In this paper, we propose wavelet transform image compression method such that an image is decomposed into multiresolutions using biorthogonal wavelet transform with linear phase response property and decomposed subbands are classified by maximum classification gain. The classified data is quantized by allocating bits in accordance with classified class informations within subbands through arbitrary set bit allocation algorithm. And then, quantized data in each subband are entropy coded. The proposed coding method is that the quantized data perform shuffling before entropy coding in order to remove sign bit plane. And the context is assigned by maximum correlation direction for bit plane coding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.153-160
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• 2004

In this paper, we propose an efficient bit loading algorithm for IEEE 802.11a wireless LAN systems. While a conventional bit loading algorithm uses the SNR value of each subcarrier, it is very difficult to estimate the exact SNR value in wireless LAN systems due to randomness of AWGN. Therefore, in order to solve this problem our proposed algorithm uses the channel frequency response instead of the SNR of each subcarrier. Through simulation results, we can obtain the performance gain of 3.5∼8㏈ at PER of 10-2 with the proposed bit loading algorithm while the conventional one obtains the performance gain of 0.5∼5㏈ at the same conditions. Also, the increased data rate can be confirmed 63Mbps. After the logic synthesis using 0.3${\mu}{\textrm}{m}$ CMOS technology, the logic gate count for the processor with proposed algorithm can be reduced by 34% in comparison with the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.998-1004
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• 2004

In this paper we propose a discrete bit-loading algorithm that maximizes the transmit bit rate using the channel information. to optimize the performance of the very high-speed digital subscriber line(VDSL) system under the constraint of a maximum transmit power for each user. When the power level of crosstalk is high, the power allocation of a user changes the crosstalk experienced by the other users in the same binder. In this case, the performance of DSL modems can be improved by jointly considering the bit and power allocation of all users Simulation results shows that the proposed method improves the performance compared With that of iterative water-filling method.