• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.124-126
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• 2021

In this study, fundus images were analyzed using an image processing algorithm for diagnosis of diabetic retinopathy, and specific areas such as hard exudate and retinal hemorrhage, which are characteristic of diabetic retinopathy disease using the bit plane technique, were extracted. We propose a system capable of automatic diagnosis by quantifying the characteristics of diabetic retinopathy based on the analyzed fundus image.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.3
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• pp.197-205
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• 2004

In this paper, we studied on the hardware implementation of a 3${\times}$3 window weighted median filter using bit-level sorting algorithm. The weighted median filter is a generalization of the median filter that is able to preserve :,harp changes in signal and is very effective in removing impulse noise. It has been successfully applied in various areas such as digital signal and video/image processing. The weighted median filters are, for the most part, based on word-level sorting methods, which have more hardware and time complexity, However, the proposed bit-serial sorting algorithm uses weighted adder tree to overcome those disadvantages. It also offers a simple pipelined filter architecture that is highly regular with repeated modules and is very suitable for weighted median filtering. The algorithm was implemented by VHDL and graphical environment in MAX＋PlusII of ALTERA. The simulation results indicate that the proposed design method is more efficient than the traditional ones.

• Journal of KIISE
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• v.44 no.5
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• pp.537-544
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• 2017

As a special form of the signed-digit representation, the NAF(non-adjacent form) minimizes the hamming weight by reducing the average density of the non-zero bits from the binary representation of the positive integer k. Due to this advantage, the NAF is used in various fields; in particular, it is actively used in cryptology. The existing NAF-conversion algorithm, however, is problematic because the conversion speed decreases when the LSB(least significant bit) frequently becomes "1" during the binary positive integer conversion process. This paper suggests a method for the improvement of the NAF-conversion speed for which the problems that occur in the existing NAF-conversion process are solved. To verify the performance improvement of the algorithm, the CPU cycle for the various inputs were measured on the ATmega128, a low-performance 8-bit microprocessor. The results of this study show that, compared with the existing algorithm, the suggested algorithm not only improved the processing speed of the major patterns by 20% or more on average, but it also reduced the NAF-conversion time by 13% or more.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.9
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• pp.99-108
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• 1997

An efficient wavelet packet algorithm to find wavelet packet quickly is presented in this paper. The top-down method maximizing the transform coding gain that is obtained from the second moment of the band is used to divide the subbands into wavelet tree. The bit allocation for each band in the tree is performed in proportion to its variance. Bands are coded by the lossless coding algorithm called the bit plane run length coding(BPRLC) and uniform quantizer. The proposed algorithm is compared with of the single tree algorithim proposed by Ramchandran and Vetterli. To verify the efficiency of our algorithm, simulations are jperformed using several sets of images. The results show us that our method reduces the execution time by about forty percent of that required by the single tree method while maintaining the comparable reconstructed image qualities.

• Journal of Information Technology Services
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• v.12 no.3
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• pp.331-343
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• 2013

In RFID systems, the anti-collision algorithm is being improved to recognize Tag's ID within recognition area of the reader quickly and efficiently. This paper focuses on Tag collision. Many studies have been carried out to resolve Tag collision. This paper proposes a new N-ary Query Tree Algorithm to resolve more than Tag collision simultaneously, according to the value of m(2 ~ 6). This algorithm can identify more tags than existing methods by treating a maximum 6 bit collision, regardless of the continuation/non-continuation Tag's ID patterns. So, it extracts maximumly different $2^6$ bit patterns per single prefix in recognition process. The performance of N-ary Query Tree Algorithm is evaluated by theoretical analysis and simulation program.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.176-181
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• 2005

This paper presents an equal bit rate control algorithm utilizing the statistical change between the previous frame and the current frame. The previous studies on the model-based rate control have focused on the models of bit rate and distortion in types of coders, in terms of the quantization parameter. The proposed algorithm improves the typical model-based rate control by updating a model parameter instead of modeling a better model of the rate and distortion. The proposed algorithm updates this model parameter by recognizing the change in statistics between the previous frame and the current frame. We implement the proposed algorithm in MPEG-4 coders and verify its performance while comparing it to the TMN8's approach (up to 0.6dB of improvement).

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.21-27
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• 2013

In this paper, we propose a low-complexity Turbo coded BICM-ID (bit-interleaved coded modulation with iterative decoding) system. A Turbo code is a powerful error correcting code with a BER (bit error rate) performance very close to the Shannon limit. In order to increase spectral efficiency of the Turbo code, a coded modulation combining Turbo code with high order modulation is used. The BER performance of Turbo-BICM can be improved by Turbo-BICM-ID using iterative demodulation and decoding algorithm. However, compared with Turbo-BICM, the decoding complexity of Turbo-BICM-ID is increased by exchanging information between decoder and demodulator. To reduce the decoding complexity of Turbo-BICM-ID, we propose a low-complexity Turbo-BICM-ID system. When compared with conventional Turbo-BICM-ID, the proposed scheme not only show similar BER performance but also reduce the decoding complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.323-330
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• 2021

Recently, the advantages of high-speed arithmetic in quantum computers have been known, and interest in quantum circuits utilizing qubits has increased. The Grover algorithm is a quantum algorithm that can reduce n-bit security level symmetric key cryptography and hash functions to n/2-bit security level. Since the Grover algorithm work on quantum computers, the symmetric cryptographic technique and hash function to be applied must be implemented in a quantum circuit. This is the motivation for these studies, and recently, research on implementing symmetric cryptographic technique and hash functions in quantum circuits has been actively conducted. However, at present, in a situation where the number of qubits is limited, we are interested in implementing with the minimum number of qubits and aim for efficient implementation. In this paper, the domestic hash function LSH is efficiently implemented using qubits recycling and pre-computation. Also, major operations such as Mix and Final were efficiently implemented as quantum circuits using ProjectQ, a quantum programming tool provided by IBM, and the quantum resources required for this were evaluated.