• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.2
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• pp.111-120
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• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.55-62
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• 2004

This paper proposes and analyzes two anti-collision algorithms in Ubiquitous ID system. We mathematically compares the performance of the proposed algorithms with that of binary search algorithm slotted binary tree algorithm using time slot, and bit-by-bit binary tree algorithm proposed by Auto-ID center. We also validated analytic results using OPNET simulation. Based on analytic result comparing the proposed Modified bit-by-bit binary tree algorithm with bit-by-bit binary tree algorithm which is the best of existing algorithms, the performance of Modified bit-by-bit binary tree algorithm is about 5% higher when the number of tags is 20, and 100% higher when the number of tags is 200. Furthermore, the performance of proposed Enhanced bit-by-bit binary tree algorithm is about 335％ and 145% higher than Modified bit-by-bit binary tree algorithm for 20 and 200 tags respectively.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.5 s.335
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• pp.47-54
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• 2005

This paper proposes and analyzes a Tag Anti-collision algorithm in RFID system. We mathematically compare the performance of the proposed algorithm with existing binary algorithms(binary search algorithm, slotted binary tree algorithm using time slot, and bit-by-bit binary tree algorithm proposed by Auto-ID center). We also validated analytic results using OPNET simulation. Based on analytic result, comparing the proposed Improved bit-by-bit binary tree algerian with bit-by-bit binary tree algorithm which is the best of existing algorithms, the performance of Improved bit-by-bit binary tree algorithm is about $304\%$ higher when the number of tags is 20, and $839\%$ higher when the number of tags is 200.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.306-317
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• 1997

This ppaer presents a bit-rate conversion system for efficient communications between 3 channel CVSD systems with different bit-rates. The proposed conversion system is implemented in the digital domain and specially, the conversion problem between 32 Kbps and 16 Kbps CVSD systems is studied. The conventional conversion system implemented in the analog domain allows signals to be easily degraded by external noises. To overcome this problem, a digital CVSD bit-rate conversion system robust to external noises is developed. the new systemdecodes CVSD bit sequences and converts sampling rates of decoded signals, then encodes signals at target bit-rates. Since linear phase property does not matter in this application, instead of FIR filters a IIR filter is employed to reduce the system complexity. Therefore, a 3 channel digital CVSD bit-rate conversion system was successfully real-time implemented using a general purpose DSP. In addition, conversion problems with unkown time constants were experimented and good experimental results were obtained.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.137-146
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• 1997

The simplest bit error detection scheme is to append a parity bit to the end of a bit sequence. In this paper an error correction technique with the use of a parity bit is proposed, and the performance of the proposed system is analyzed. The error probability of the proposed system is compared with the output of computer simulation of the proposed system. It is also compared with the error probability of error at BPSK system, and the signal-to-noise ratio gain is showed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12B
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• pp.1091-1099
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• 2003

Korea National Intelligence Service has been issued on K4 Firewall Certificates, and these K4 Firewalls has b een installing all Korean public organizer. I would evaluate the performance tests between the before setting and the after setting of Packet Filtering, NAT, Proxy, and Authentication services on functions of Solaris K4 Firewall System. Also I had been created by performance test between existing 32 bit and latest 64 bit K4 Firewall System on Solaris Operating System, So that the result of improved more two times passed rate on 64bit than 32bit on Solaris K4 Firewall System, At finally, I would conclude that the change direction will be useful for research and development on K4 Firewall System and Korean Firewall System which is a very competitive system in the world.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.71-73
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• 1998

새로운 DEC Alpha, MINPS R40001[1], PowerPC등과 같은 64-bit 마이크로프로세서는 운영체제와 응용프로그램에 매우 광활한 64-bit 주소공간(wide address system)을 제공한다. 64-bit 주소공간은 중소규모 분산 컴퓨터 시스템의 모든 데이터를 포함할 수 있는 크기이다. 이 64-bit 주소공간은 32-bit 주소공간과 다른 방법으로 활용하는 것을 가능하게 해주었다. 지금까지의 시스템과는 달리 WAS(wide address system)에서는 모든 프로세서들이 하나의 주소공간을 공유함으로서 프로세서간 자료의 공유 및 통신이 간편하게 이루어 질 수 있다. 공유된 광활한 64-bit 주소공간의 상용방안은 WAS 시스템 연구에서 매우 중요하다. 본 논문에서는 WAS 시스템의 보다 구현하기 쉬운 64-bit 주소공간의 설계에 대해서 제안한다.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.272-274
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel found and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in $10^{-1}\sim10^{-5}$ of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.443-446
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• 2005

In this paper, we analyses transmission performance of communication security(COMSEC) bit synchronization information over the single channel ground and airborne radion system in variable message format system. Experimental results demonstrate the robust characteristics of the COMSEC bit synchronization information in 10-1 $\~$ 10-5 of bit error channel and the relationship of time duration of bit synchronization and probability of synchronization detection.