• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.34-40
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• 1992

This paper shows a new relational formula of multiplexing gain versus variable input bit rates useful for designing Nx1 ATM(Asynchronous Transfer Mode) multiplexer which mixes several asynchronous bit streams with different transmission rates. The relation between multiplexing gain and input bit stream speeds is derived from the occupied mean lenght(the width per unit time) of cells and the occupation probability of the number of cells at an arbitrary instant when the rates of the periodic cell strams change randomly. And the relation between multiplexing gain and variable bit rates from different number of input bit streams is analyzed accordingly. Under the condition of unlimited multiplexing speed, the more number of input bit streams increases, the bigger the multiplexing gain becomes. While for the case which restricts the multiplexing speed to a limited value, the multiplexing gain becomes smaller contrarily as the number of input bit streams continues too invrease beyond a boundary value. It is shown that for designing an ATM multiplexer according to the latter case, the combination of input bit streams should be determined such as its total bit rate is lower thean, but most apprpaximate to, the multiplexed output speed. Also the general formula evaluating the most significant parameters which should be needed to design the multiplexer is derived.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.1040-1057
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• 2014

In this paper, a new bit rate estimation scheme is proposed to determine the bit rate for each subclass in an MPEG-2 TS to H.264/AVC transcoder after dividing an input MPEG-2 TS sequence into several subclasses. Video format transcoding in conventional IPTV and Smart TV services is a time-consuming process since the input sequence should be fully transcoded several times with different bit-rates to decide the bit-rate suitable for a service. The proposed scheme can automatically decide the bit-rate for the transcoded video sequence in those services which can be stored on a video streaming server as small as possible without losing any subject quality loss. In the proposed scheme, an input sequence to the transcoder is sub-classified by hierarchical clustering using a parameter value extracted from each frame. The candidate frames of each subclass are used to estimate the bit rate using a statistical analysis and a mathematical model. Experimental results show that the proposed scheme reduces the bit rate by, on an average approximately 52% in low-complexity video and 6% in high-complexity video with negligible degradation in subjective quality.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.958-964
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• 2007

In this paper, we derive the relationship between the bit error probability (BEP) of maximum a posteriori (MAP) bit detection and the bit minimum mean square error (MMSE), that is, the BEP is greater than a quarter of the bit USE and less than a half of the bit MMSE. By using this result, the lower and upper bounds of the derivative of the mutual information are derived from the BEP and the lower and upper bounds are easily obtained in the multiple-input multiple-output (MIMO) communication systems with the bit-linear linear-dispersion (BLLD) codes in the Gaussian channel.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.18-26
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• 2009

When channel state information (CSI) is available at the transmitter, the system throughput can be enhanced by adaptive transmissions and opportunistic multiuser scheduling. In this paper, we consider multiple-input multiple-output (MIMO) systems employing bit-interleaved coded orthogonal frequency division multiplexing (BIC-OFDM). We first propose a bit-loading algorithm based on the Levin-Campello algorithm for the BIC-OFDM. Then we will apply this algorithm to the MIMO system with a finite set of constellations, by reassigning residual power on each stream Simulation results show that proposed bit-loading scheme which takes the residual power into account improves the system performance especially at high signal-to-noise ratio (SNR) range.

• ETRI Journal
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• v.24 no.6
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• pp.462-464
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• 2002

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.197-200
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• 2002

In this paper, presents a 1.8V 8-bit 300MSPS CMOS Subranging Analog to Digital Converter (ADC) with a novel reference multiplex is described. The proposed hか converter is composed of Sub A/D Converter block, MUX (Multiplexer) block and digital block. In order to obtain a high-speed operation, further, a novel dynamic latch, an encoder of novel algorithm and a MUX block are proposed. As a result, this A/D Converter is operated 100MHz input frequence by 300MHz sampling rate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.