• 전자공학회논문지A
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• 제29A권8호
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• pp.34-40
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• 1992

This paper shows a new relational formula of multiplexing gain versus variable input bit rates useful for designing Nx1 ATM(Asynchronous Transfer Mode) multiplexer which mixes several asynchronous bit streams with different transmission rates. The relation between multiplexing gain and input bit stream speeds is derived from the occupied mean lenght(the width per unit time) of cells and the occupation probability of the number of cells at an arbitrary instant when the rates of the periodic cell strams change randomly. And the relation between multiplexing gain and variable bit rates from different number of input bit streams is analyzed accordingly. Under the condition of unlimited multiplexing speed, the more number of input bit streams increases, the bigger the multiplexing gain becomes. While for the case which restricts the multiplexing speed to a limited value, the multiplexing gain becomes smaller contrarily as the number of input bit streams continues too invrease beyond a boundary value. It is shown that for designing an ATM multiplexer according to the latter case, the combination of input bit streams should be determined such as its total bit rate is lower thean, but most apprpaximate to, the multiplexed output speed. Also the general formula evaluating the most significant parameters which should be needed to design the multiplexer is derived.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권3호
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• pp.1040-1057
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• 2014

In this paper, a new bit rate estimation scheme is proposed to determine the bit rate for each subclass in an MPEG-2 TS to H.264/AVC transcoder after dividing an input MPEG-2 TS sequence into several subclasses. Video format transcoding in conventional IPTV and Smart TV services is a time-consuming process since the input sequence should be fully transcoded several times with different bit-rates to decide the bit-rate suitable for a service. The proposed scheme can automatically decide the bit-rate for the transcoded video sequence in those services which can be stored on a video streaming server as small as possible without losing any subject quality loss. In the proposed scheme, an input sequence to the transcoder is sub-classified by hierarchical clustering using a parameter value extracted from each frame. The candidate frames of each subclass are used to estimate the bit rate using a statistical analysis and a mathematical model. Experimental results show that the proposed scheme reduces the bit rate by, on an average approximately 52% in low-complexity video and 6% in high-complexity video with negligible degradation in subjective quality.

• 전자공학회논문지
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• 제49권11호
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• pp.149-156
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• 2012

디지털 입력 D급 증폭기는 보청기에서 사용되고 있으며 D급 증폭기는 디지털 회로와 아날로그 회로로 구성되어진다. 아날로그 회로는 가청 주파수 대역에서 잡음을 억제하고 디지털 입력을 아날로그 신호로 변환한다. 본 논문에서 제안한 인터폴레이티드 디지털 델타-시그마 변조기는 디지털 신호 처리기의 출력 신호를 D/A 변조기 입력에 적합하도록 데이터를 변조시킨다. 디지털 필터는 16-bit, 25-kbps 펄스 코드 변조 신호를 16-bit, 50-kbps 신호로 보간 작업을 한다. 이 보간 필터 출력은 3차 디지털 델타-시그마 변조기를 통하여 노이즈 쉐이핑(noise shaping) 처리된다. 최종적으로, 1.5-bit, 3.2-Mbps 신호가 D/A 변조기 입력으로 인가된다.

• 한국통신학회논문지
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• 제32권10A호
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• pp.958-964
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• 2007

이 논문은 maximum a posteriori (MAP) 비트 검출(bit detection)의 비트 오류 확률 (bit error probability: BEP)과 비트 최소 평균 제곱 오류(bit minimum mean square error: bit MMSE)사이의 관계를 유도한다. BEP는 bit MMSE의 1/4 보다 크고 1/2보다 작음을 유도한다. 이 결론을 이용하면 bit-linear linear-dispersion (BLLD) 부호를 적용한 다중 입출력 (multiple-input multiple-output: MIMO) 통신 시스템에서 가우시안 채널의 mutual information의 미분 값의 하한과 상한을 BEP로부터 얻을 수 있고 나아가서 mutual information의 하한과 상한을 구할 수 있다.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• 대한전자공학회논문지TC
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• 제46권2호
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• pp.18-26
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• 2009

송신단에서 채널 상태 정보를 알 수 있는 경우, 적응 알고리즘을 통한 전송 및 다중사용자 스케줄링을 통해 시스템 전송률을 향상시킬 수 있다. 본 논문에서는 비트 인터리버와 결합한 부호화된 직교 주파수 다중 분할 (BIC-OFDM; Bit-Interleaved Coded Orthogonal frequency Division Multiplexing) 기법을 기반으로 하는 다중안테나 (MIMO; Multiple-Input Multiple Output) 시스템을 고려한다. 먼저 Levin-Campello 알고리즘을 개선한 비트 로딩 (bit-loading) 기법을 제안하고, 이를 다중안테나 시스템으로 확장하여 한정된 개수의 신호 성상을 사용하는 데 따르는 잔여 파워 문제를 극복하는 알고리즘을 제시한다. 실험 결과는 제안하는 기법이 시스템 성능을 개선시키며 특히 높은 신호 대 잡음비 (SNR; Signal-to-Noise Ratio) 영역에서 기존의 기법에 비하여 큰 성능 이득을 제공함을 보여준다.

• ETRI Journal
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• 제24권6호
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• pp.462-464
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• 2002

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial-to-parallel and parallel-to-serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial-to-parallel and 8 bit or 16 bit parallel-to-serial conversion takes place in data blocks of the selected data length.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.197-200
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• 2002

In this paper, presents a 1.8V 8-bit 300MSPS CMOS Subranging Analog to Digital Converter (ADC) with a novel reference multiplex is described. The proposed hか converter is composed of Sub A/D Converter block, MUX (Multiplexer) block and digital block. In order to obtain a high-speed operation, further, a novel dynamic latch, an encoder of novel algorithm and a MUX block are proposed. As a result, this A/D Converter is operated 100MHz input frequence by 300MHz sampling rate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.706-711
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• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• 조명전기설비학회논문지
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• 제29권3호
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.