• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.2
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• pp.123-129
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• 2002

5-bit broadband MMIC phase shifter has been designed and fabricated. For the broadband performance, 11.25$^{\circ}$, 22.5$^{\circ}$, 45$^{\circ}$ and 90$^{\circ}$ bit have been designed with Lange coupler and 180$^{\circ}$ bit has been implemented by using shorted coupled line with Lange coupler and $\pi$-network of transmission line. Due to Lange coupler with large size, the Lange couplers have been folded far circuit size reduction. Low loss PIN diode has been utilized as a switch for each bit. Fabricated 5-bit broadband phase shifter shows the measured results that RMS phase error of 5 major phases is 3.5$^{\circ}$, maximum insertion loss is 12.5 dB, and maximum input and output return loss are 7 dB and 10 dB, respectively. The size of fabricated phase shifter is 6.5$\times$5.3 $ extrm{mm}^2$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.104-110
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• 2006

The advantage of the DSM which employ multi-bit quantizer is the increased SNR at the modulator's output. Typically 6 dB improvement is effected for every one additional bit. But multi-bit quantizer evidently requires multi-bit DAC in the feedback loop. The integral linearity error of the feedback DAC has direct impact upon the system performance and degraded SNR of the system. In order to mitigate the negative impact the DAC has on the system performance, many DEM(Dynamic Element Matching) schemes has been proposed. Among the proposed schemes, four schemes(DER,CLA,ILA,DWA) are explained and its performance has been compared. DWA(Data Weighted Averaging) method shows the best performance of the all.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.1040-1057
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• 2014

In this paper, a new bit rate estimation scheme is proposed to determine the bit rate for each subclass in an MPEG-2 TS to H.264/AVC transcoder after dividing an input MPEG-2 TS sequence into several subclasses. Video format transcoding in conventional IPTV and Smart TV services is a time-consuming process since the input sequence should be fully transcoded several times with different bit-rates to decide the bit-rate suitable for a service. The proposed scheme can automatically decide the bit-rate for the transcoded video sequence in those services which can be stored on a video streaming server as small as possible without losing any subject quality loss. In the proposed scheme, an input sequence to the transcoder is sub-classified by hierarchical clustering using a parameter value extracted from each frame. The candidate frames of each subclass are used to estimate the bit rate using a statistical analysis and a mathematical model. Experimental results show that the proposed scheme reduces the bit rate by, on an average approximately 52% in low-complexity video and 6% in high-complexity video with negligible degradation in subjective quality.

• Journal of Information Technology Services
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• v.12 no.1
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• pp.1-14
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• 2013

The government has implemented operating the bus information terminal (hereinafter, 'BIT') to use by building it at a major bus station to solve the problem of traffic congestion. Busan Metropolitan City has been continuously expanding the installation of 'BIT' since 2003. However, there are few research on the factor to use and satisfaction survey on 'BIT' from the perspective of the users. This study, in an effort to inquire into the 'BIT' utilization factor and its vitalization plan, conducted a face to face survey of 172 citizens who had the experience in the 'BIT'. The result of the data analysis showed that usability, convenience, and availability were the critical factors for a BIT use. In addition, the general intention to use 'BIT' was found to be very high as much as 90.7%. The contributions of this study are as follows. The academic contributions is that it proved the relationship between usability, convenience and the intention to use suggested by the information technology acceptance model is supported even in case of 'BIT.' For the practitioners this study provides ground data for a local government to make a plan of a BIT extension.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.17-25
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• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.57-62
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• 2011

This paper presents a study on the performance analysis on probability of bit error for wavelet in 4-ary SWSK system. The formula for the bit error probability in 4-ary SWSK system was derived from the conventional method. This paper experimentally implements the probability of bit error for Daubechies, Biorthogonal, Coiflet and Symlet wavelet using the conventional formula of bit error probability. Additionally, the performance of bit error probability is analyzed for the period and the number of wavelet taps. Based on the results, we confirmed that the performance of Coiflet and Symlet wavelet for the probability of bit error is superior to the other wavelet, and their probability of bit error are similar.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.2
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• pp.111-120
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• 2012

Built-In-Test is a design feature in more and more advanced weapon system. During development test and evaluation(DT&E) it is critical that the BIT system be evaluated. The BIT system is an integral part of the weapon system and subsystem. Built-In-Test assists in conducting on system and subsystem failure detection and isolation to the Line Replaceable Unit(LRU). This capability reduces the need for highly skilled personnel and special test equipment at organizational level, and reduces maintenance down-time of system by shortening Total Corrective Maintenance Time. During DT&E of weapon system the objective of BIT system evaluation is to determine BIT capabilities achieved and to identify deficiencies in the BIT system. As a result corrective actions are implemented while the system is still in development. Through the use of the reiterative BIT evaluation the BIT system design was corrected, improved, or updated, as the BIT system matured.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.8B
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• pp.1197-1203
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• 2010

A strength of BitTorrent, which is widely used for file sharing today, is due to its peer selection mechanism which is designed to encourage peers to contribute data. In the peer selection phase in BitTorrent, peers to upload the file in a swarm are selected by determining which peers upload the most to themselves. However, the number of peers to upload (i.e., number of unchoked peers) is fixed to four in its peer selection mechanism of BitTorrent, which yields inefficiency because the situation of the swarm may vary frequently (e.g., number of peers in the swarm, download rates, and upload rates). In this paper, we analyze the swarming system performance when the number of unchoked in BitTorrents is not static, but dynamic. For empirical investigation, we established a testbed in Seoul National University by modifying an open-source BitTorrent client, which is popular. Through our experiments, we show that an adaptive mechanism to adjust the number of unchoked peers considering the situation of the swarm is needed to improve the performance of BitTorrent.