• Title/Summary/Keyword: binary processing

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A Study on Binary Image Compression Using Morphological Skeleton (수리 형태학적 세선화를 이용한 이진 영상 압축)

  • 정기룡
    • Journal of the Korean Institute of Navigation
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    • v.19 no.3
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    • pp.21-28
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    • 1995
  • Mathematical morphology skeleton image processing makes many partial skeleton image planes from an original binary image. And the original binary image can be reconstructed without any distortion by summing the first partial skeleton image plane and each dilated partial skeleton image planes using the same structuring element. Especially compression effects of Elias coding to the morphological globally minimal skeleton(GMS) image, is better than that of PCX and Huffman coding. And then this paper proposes mathematical morphological GMS image processing which can be applied to a binary image transmitting for facimile and big size(bigger than $64{\times}64$ size) bitmap fonts storing in a memory.

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On a Multiple-cycle Binary Sequence Genrator Based on S-box (S-box 형태의 다 수열 발생기에 관한 연구)

  • Lee, Hun-Jae
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.5
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    • pp.1474-1481
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    • 2000
  • The number of keystream cycle sequences has been proposed as a characteristic of binary sequence generator for cryptographic application, but in general the most of binary sequence generators have a single cycle. On the other hand, S-box has been used to block cipher for a highly nonlinear element and then we apply it to the stream cipher with a high crypto-degree. In this paper, we propose a multiple-cycle binary sequence generator based on S-box which has a high nonlinearity containing SAC property and analyze its period, linear complexity, randomness and the number of keystream cycle sequences.

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Design and Development of Electronic Attendance-absence Recording System Using Binary XML (Binary XML을 이용한 전자출결시스템 설계 및 개발)

  • Lee, Jaekun;Yeom, Saehun;Bang, Hyeja
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.11 no.3
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    • pp.11-19
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    • 2015
  • Due to recent development in mobile devices, the mobile device utilization and many related applications have been increasing. Most of initial applications on mobile devices just showed simple information, but now they processes huge data. However, smart devices have certain limitations in processing massive data. Especially, if the size of data increases, the speed of data processing adversely decreases, so the performance of programs also decreases. If hardware specification of the mobile devices is not enough to handle it, response time will be drastically delayed. To overcome these drawbacks, most of application running on mobile devices communicate with their servers to manage data. XML is a proper language for data communication to send and receive data between servers and mobile devices, because it defines rules of document's format and it is a textual data format and small-sized language. However, mobile devices have limitation such as memory, CPU and wireless network to process huge data and XML also takes a lot of time to communicate with servers and devices and handle data, so it could be overhead in service time. Binary XML is an alternative of performance improvement in data processing, which has XML's benefits and minimizes the XML size by binary coding. However, most of binaryXML which are used on applications don't fit on mobile applications. In this paper, we surveyed many kinds of binaryXML, compared merits and demerits to find a binaryXML for mobile applications. We propose how to use binary XML and implemented an electronic attendance system using binary XML to overcome the limitation of XML and to reduce the load of data communications between servers and devices.

A Design of Correlator with the PBS Architecture in Binary CDMA System (Binary CDMA 시스템에서 PBS 구조를 가지는 코릴레이터 설계)

  • Lee, Seon-Keun;Jeong, Woo-Yeol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.3 no.3
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    • pp.177-182
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    • 2008
  • Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

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A Study on Binary CDMA System Correlator Design for High-Speed Acquisition Processing (고속 동기 처리를 위한 Binary CDMA 시스템 코릴레이터 설계에 관한 연구)

  • Lee, Seon-Keun;Jeong, Woo-Yeol
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.1 s.45
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    • pp.155-160
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    • 2007
  • Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

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Analysis of a binary feedback switch algorithm for the ABR service in ATM networks (ATM망에서 ABR 서비스를 위한 이진 피드백 스위치 알고리즘의 성능 해석)

  • 김동호;안유제;안윤영;박홍식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.1
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    • pp.162-172
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    • 1997
  • In this paper, we investigated the performance of a binary feedback switch algorithm for the ABR(Available Bit Rate) service in ATM networks. A binary feedback switch is also called EFCI(Explicit Forward Congestion Indication) switch and can be classificed into input cell processing(IP) scheme according to processing methods for the EFCI bit in data-cell header. We proposed two implementation methods for the binary feedback switch according to EFCI-bit processing schemes, and analyzed the ACR(Allowed Cell Rate) of source and the queue length of switch for each scheme in steady state. In addition, we derived the upper and lower bounds for maximum and minimum queue lengths, respectively, and investigated the impact of ABR parameters on the queue length.

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Android library vulnerability analysis using binary lifting (Binary lifting을 이용한 안드로이드 라이브러리 취약점 분석)

  • Lee, Sung-Won;Youn, Jonghee
    • Annual Conference of KIPS
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    • 2020.05a
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    • pp.290-291
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    • 2020
  • 안드로이드 OS는 대중적이고 중요한 시스템으로 자리 잡았고, 이에 따른 다양한 연구도 진행 중이다. 본 논문에서는 보안측면에서의 취약점 분석 방법을 제시하여, 각종 보안 위협을 예방하는데 기여하고자 한다. 안드로이드 라이브러리를 대상으로 Binary Lifting 기술을 사용하여 코드기반(LLVM IR) 퍼징을 진행하는, 취약점 분석 과정을 설계 수행한다.

CMOS Binary Image Sensor Using Double-Tail Comparator with High-Speed and Low-Power Consumption

  • Kwen, Hyeunwoo;Jang, Junyoung;Choi, Pyung;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.2
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    • pp.82-87
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    • 2021
  • In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

Binary Mask Criteria Based on Distortion Constraints Induced by a Gain Function for Speech Enhancement

  • Kim, Gibak
    • IEIE Transactions on Smart Processing and Computing
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    • v.2 no.4
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    • pp.197-202
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    • 2013
  • Large gains in speech intelligibility can be obtained using the SNR-based binary mask approach. This approach retains the time-frequency (T-F) units of the mixture signal, where the target signal is stronger than the interference noise (masker) (e.g., SNR > 0 dB), and removes the T-F units, where the interfering noise is dominant. This paper introduces two alternative binary masks based on the distortion constraints to improve the speech intelligibility. The distortion constraints are induced by a gain function for estimating the short-time spectral amplitude. One binary mask is designed to retain the speech underestimated (T-F) units while removing the speech overestimated (T-F)units. The other binary mask is designed to retain the noise overestimated (T-F) units while removing noise underestimated (T-F) units. Listening tests with oracle binary masks were conducted to assess the potential of the two binary masks in improving the intelligibility. The results suggested that the two binary masks based on distortion constraints can provide large gains in intelligibility when applied to noise-corrupted speech.

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An efficient search of binary tree for huffman decoding based on numeric interpretation of codewords

  • Kim, Byeong-Il;Chang, Tae-Gyu;Jeong, Jong-Hoon
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.133-136
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    • 2002
  • This paper presents a new method of Huffman decoding which gives a significant improvement of processing efficiency based on the reconstruction of an efficient one-dimensional array data structure incorporating the numeric interpretation of the accrued codewords in the binary tree. In the Proposed search method, the branching address is directly obtained by the arithematic operation with the incoming digit value eliminating the compare instruction needed in the binary tree search. The proposed search method gives 30% of improved Processing efficiency and the memory space of the reconstructed Huffman table is reduced to one third compared to the ordinary ‘compare and jump’ based binary tree. The experimental result with the six MPEG-2 AAC test files also shows about 198% of performance improvement compared to those of the widely used conventional sequential search method.

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