• Korean Management Science Review
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• v.28 no.2
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• pp.53-62
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• 2011

The objective of this paper is to propose a Binary Particle Swarm Optimization(BPSO) for design of reporting cell management system. The assignment of cells to reporting or non-reporting cells is an NP-complete problem having an exponential complexity in the Reporting Cell Location Management(RCLM) system. The number of reporting cells and which cell must be reporting cell should be determined to balance the registration(location update) and search(paging) operations to minimize the cost of RCLM system. Experimental results demonstrate that BPSO is an effective and competitive approach in fairly satisfactory results with respect to solution quality and execution time for the optimal design of location management system.

• Journal of Biosystems Engineering
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• v.21 no.3
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• pp.315-324
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• 1996

This study was one of a series of studies on application of machine vision and image processing to extract the geometrical features of plants and to analyze plant growth. Several algorithms were developed to measure morphological properties of plants and describing the growth development of in-situ lettuce(Lactuca sativa L.). Canopy, centroid, leaf density and fractal dimension of plant were measured from a top viewed binary image. It was capable of identifying plants by a thinning top viewed image. Overlapping the thinning side viewed image with a side viewed binary image of plant was very effective to auto-detect meaningful nodes associated with canopy components such as stem, branch, petiole and leaf. And, plant height, stem diameter, number and angle of branches, and internode length and so on were analyzed by using meaningful nodes extracted from overlapped side viewed images. Canopy, leaf density and fractal dimension showed high relation with fresh weight or growth pattern of in-situ lettuces. It was concluded that machine vision system and image processing techniques are very useful in extracting geometrical features and monitoring plant growth, although interactive methods, for some applications, were required.

• Industrial Engineering and Management Systems
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• v.16 no.1
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• pp.141-153
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• 2017

A binary integer programming model is proposed for a complex timetabling problem in a university faculty which conducts various degree programs. The decision variables are defined with fewer dimensions to economize the model size of large scale problems and to improve modeling efficiency. Binary matrices are used to incorporate the relationships between the courses and students, and the courses and teachers. The model includes generally applicable constraints such as completeness, uniqueness, and consecutiveness; and case specific constraints. The model was coded and solved using Open Solver which is an open-source optimizer available as an Excel add-in. The results indicate that complicated timetabling problems with large numbers of courses and student groups can be formulated more efficiently with fewer numbers of variables and constraints using the proposed modeling framework. The model could effectively generate timetables with a significantly lower number of work hours per week compared to currently used timetables. The model results indicate that the particular timetabling problem is bounded by the student overlaps, and both human and physical resource constraints are insignificant.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.316-321
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• 2000

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

• Communications for Statistical Applications and Methods
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• v.12 no.1
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• pp.207-216
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• 2005

A binary segmentation procedure is a simple recursive approach to detect clusters and provide inferences for the study space when the shape of the clusters and the number of clusters are unknown. The procedure involves a sequence of nested hypothesis tests of a single cluster versus a pair of distinct clusters. The size and the shape of the clusters evolve as the procedure proceeds. The procedure allows for various growth clusters and for arbitrary baseline densities which govern the form of the hypothesis tests. A real tree data is used to highlight the procedure.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.215-217
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• 2006

This paper presents an area efficient 8-bit current digital to analog convector (DAC) which is applied to 240 channels Active Matrix - Organic Light Emitting Diode (AMOLED) data driver. The proposed circuit constitutes 4-bit binary weighted current DAC and 4-bit switched capacitor cyclic DAC. The proposed DAC has about 70% smaller area than that of the typical binary weighted current DAC. We overcome sampling time by reducing the number of repetition phases so that it can display 8-bit gray scale image.

• Journal of ILASS-Korea
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• v.11 no.2
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• pp.75-80
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• 2006

The present article proposes a new droplet collision model including the stretching separation regime and the formation of satellite droplets. The new model consists of several equations to calculate the post-collision characteristics of colliding droplets and satellite droplets. These equations are derived from the energy balance of droplets between before and after collision. For binary collision of water droplets, the new model shows good agreement with experimental data far the number of satellite droplets.

• ETRI Journal
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• v.24 no.5
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• pp.373-380
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• 2002

This paper presents a new method for a visual cryptography scheme that uses phase masks and an interferometer. To encrypt a binary image, we divided it into an arbitrary number of slides and encrypted them using an XOR process with a random key or keys. The phase mask for each encrypted image was fabricated nuder the proposed phase-assignment rule. For decryption, phase masks were placed on any path of the Mach-Zehnder interferometer. Through optical experiments, we confirmed that a secret binary image that was sliced could be recovered by the proposed method.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.22 no.4
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• pp.440-451
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• 1998

An experimental study has been conducted to investigate solidification of NH$_{4}$CI-H$_{2}$0 mixtures inside a vertical rectangular enclosure. Solidification process is visualized by the shadowgraph method. Emphasis is placed on the effect of solidification parameters such as the aspect ratio, cooling wall temperature and initial composition. The aspect ratio shows a dominant effect on the number and developing time of the double diffusive layers which reveals the relative strength of solutal convection to thermal convection. Similar flow pattern is observed when the concentration difference between interdendritic liquid and the pure liquid which drives solutal convection is the same regardless of the different cooling wall temperature and initial concentration.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.