• Honam Mathematical Journal
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• v.28 no.4
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• pp.521-531
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• 2006

In this paper, we construct a procedure of Maple programming for (0, 1)-matrix with a prescribed permanent, $1,2,...,2^{n-1}$. An application of such construction is given, and we obtain the some results of (0, 1)-matrices with the permanent less than or equal to n! by replacing elements 0's by 1's.

• Journal of the Korean Mathematical Society
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• v.36 no.6
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• pp.1181-1190
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• 1999

Zero-term rank of a matrix is the minimum number of lines (rows or columns) needed to cover all the zero entries of the given matrix. We characterized the linear operators that preserve zero-term rank of the m×n matrices over binary Boolean algebra.

• East Asian mathematical journal
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• v.26 no.5
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• pp.649-654
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• 2010

A positive definite Hermitian lattice is said to be 2-universal if it represents all positive definite binary Hermitian lattices. We find some finiteness theorems which ensure 2-universality of Hermitian lattices over several imaginary quadratic number fields.

• Journal of the Korea Society of Computer and Information
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• v.18 no.4
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• pp.123-129
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• 2013

The performance and practicality of cryptosystem for encryption, decryption, and primality test are primarily determined by the implementation efficiency of the modular exponentiation of $a^b$ (mod m). To compute $a^b$ (mod m), the standard binary squaring (square-and-multiply) still seems to be the best choice. However, in large b bits, the preprocessed n-ary, ($n{\geq}2$ method could be more efficient than binary squaring method. This paper proposes a square-and-divide and unpreprocessed n-ary square-and-divide modular exponentiation method. Results confirmed that the square-and-divide method is the most efficient of trial number in a case where the value of b is adjacent to $2^k+2^{k-1}$ or to. $2^{k+1}$. It was also proved that for b out of the beforementioned range, the unpreprocessed n-ary square-and-divide method yields higher efficiency of trial number than the general preprocessed n-ary method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.348-359
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• 1989

The multitree pattern recognition algorithm proposed by [1] and [2] is modified in order to improve its performance. The basic idea of the multitree pattern classification algorithm is that the binary dceision tree used to classify an unknow pattern is constructed for each feature and that at each stage, classification rule decides whether to classify the unknown pattern or to extract the feature value according to the feature ordet. So the feature ordering needed in the calssification procedure is simple and the number of features used in the classification procedure is small compared with other classification algorithms. Thus the algorithm can be easily applied to real pattern recognition problems even when the number of features and that of the classes are very large. In this paper, the wighting factor assignment scheme in the decision procedure is modified and various classification rules are proposed by means of the weighting factor. And the branch and bound method is applied to feature subset selection and feature ordering. Several experimental results show that the performance of the multitree pattern classification algorithm is improved by the proposed scheme.

• The Journal of the Korea Contents Association
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• v.15 no.2
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• pp.11-20
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• 2015

In this paper, we develop an intelligent mobile surveillance system based on binary CDMA for the unmanned automatic tracking and surveillance. That is, we implement a intelligent surveillance system using the binary CDMA wireless communication technology which is applied the merit of CDMA and TDMA on it complexly. This system is able to monitor the site of the accident on network in real time and process the various situations by implementing the security surveillance system. This system pursues an object by the 360-degree using camera, expands image using a PTZ(Pan/Tilt/Zoom) camera zooming function, identifies the mobile objects image within a screen and transfers the identified image to the remote site. Finally, we show the efficiency of the implemented system through the simulation of the controlled situations, such as tracking coverage on objects, object expansion, object detection number, monitoring the remote transferred image, number of frame per second by the image output signal etc..

• Journal of Korea Multimedia Society
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• v.17 no.9
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• pp.1070-1075
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• 2014

Due to a number of illegal copied videos, many video content markets have been threatened. Since this copied videos have intercepted the profits of the content holders, content developers lose the will to generate new contents. Therefore, video copy detection approaches have been developed to protect the copyrights of video contents. However, many illegal uploader who generate copied videos used video transformations to avoid video copy detection systems. Among of the video transformations, rotation and flipping did not distorted the quality of video contents. Thus, these two video transformations were adopt to generate copied video. In order to detect rotated or flipping copy videos, rotation and flipping robust region binary pattern (RFR) recently was proposed. But, this RFR has a weakness according to rotated angles. Therefore, in order to overcome this problem, multi region binary patterns are proposed in this paper. The proposed method has the similar performance with the original RFR. But, it showed much higher efficiency for memory spaces.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.579-587
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• 2014

This paper presents a variable gain amplifier (VGA) for an analog front-end (AFE) of ultrasound medical imaging. This VGA has a closed-loop topology and shows a 37-dB-linear characteristic with a single-stage amplifier. It consists of an op-amp, a non-binary-weighted capacitor array, and a gain-control block. This non-binary-weighted capacitor array reduces the required number of capacitors and the complexity of the gain-control block. The VGA has been fabricated in a 0.35-mm CMOS process. This work gives the largest gain range of 37 dB per stage, the largest P1 dB of 9.5 dBm at the 3.3-V among the recent VGA circuits available in the literature. The voltage gain is controlled in the range of [-10, 27] dB in a linear-in-dB scale with 16 steps by a 4-bit digital code. The VGA has a bandpass characteristic with a passband of [20 kHz, 8 MHz].

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.501-507
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• 2005

This paper proposes a Hybrid Random PWM(HRPWM) technique using a LF2407 DSP board in order to spread the power spectra of an induction motor. The proposed method is composed to the PRBS (Pseudo-Random Binary Sequence) with the Lead-Lag random bit and the random triangular carrier for the logical comparison. Also, a DSP generates the random number, the PRBS and the three-phase reference signal, a MAX038 chip operating as frequency modulator generates the random triangular carrier. For verification of the proposed method, the experiments were conducted with a three-phase adjustable speed a.c drives, and the results of simulations and experiments are presented.