• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2006.11a
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• pp.407-410
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• 2006

This study describes a simulation of two-dimensional bubble forming and motion by the Lattice Boltzmann Method with the phase field equation. The free energy model is used to treat the interfacial force and deformation of binary fluids system, drawn into a T-junction the micro channel. A numerical simulation of a binary flow in a cross-junction channel is carried out by using the parallel computation method. The aim in this investigation is to examine the applicability of LBM to numerical analysis of binary fluid separation and motion in the micro channel.

• Journal of the Optical Society of Korea
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• v.18 no.1
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• pp.82-88
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• 2014

A binary-coupled dipole approximation (BCDA) is described for designing metal nanoparticles with nonperiodic structures in one, two, and three dimensions. This method can be used to simulate the variation of near- and far-field properties through the interactions of metal nanoparticles. An advantage of this method is in its combination with the binary particle swarm optimization (BPSO) algorithm to find the best array of nanoparticles from all possible arrays. The BPSO algorithm has been used to design an array of plasmonic nanospheres to achieve maximum absorption, scattering, and extinction coefficient spectra. In BPSO, a swarm consists of a matrix with binary entries controlling the presence ('1') or the absence ('0') of nanospheres in the array. This approach is useful in optical applications such as solar cells, biosensors, and plasmonic nanoantennae, and optical cloaking.

• Bulletin of the Korean Mathematical Society
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• v.60 no.3
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• pp.829-844
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• 2023

In this paper, we present a new construction for self-dual codes that uses the concept of double bordered construction, group rings, and reverse circulant matrices. Using groups of orders 2, 3, 4, and 5, and by applying the construction over the binary field and the ring F₂ + uF₂, we obtain extremal binary self-dual codes of various lengths: 12, 16, 20, 24, 32, 40, and 48. In particular, we show the significance of this new construction by constructing the unique Extended Binary Golay Code [24, 12, 8] and the unique Extended Quadratic Residue [48, 24, 12] Type II linear block code. Moreover, we strengthen the existing relationship between units and non-units with the self-dual codes presented in [10] by limiting the conditions given in the corollary. Additionally, we establish a relationship between idempotent and self-dual codes, which is done for the first time in the literature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1267-1275
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• 2017

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency.

• The Journal of Korean Association of Computer Education
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• v.5 no.4
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• pp.43-52
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• 2002

A theory of binary wavelets which are performed over binary field has been recently proposed. Binary wavelet transform (BWT) of binary images can be used as an alternative to the real-valued wavelet transform of binary images in image processing applications such as compression, edge detection, and recognition. The BWT, however, requires large amount of computations for binary wavelet reconstruction since its operation is accomplished by matrix multiplication. In this paper, an efficient binary wavelet reconstruction method which utilizes filtering operation instead of matrix multiplication is presented. Experimental results show that the proposed algorithm can significantly reduce the computational complexity of the BWT. For the reconstruction of an $N{\times}N$ image, the proposed technique requires only $2MN^2$ multiplications and $2N(M-1)^2$ additions when the filter length M, while the BWT needs $2N^3$ multiplications and $2N(N-1)^2$ additions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12B
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• pp.1103-1111
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• 2008

Internet routers forward an incoming packet to an output port toward its final destination through IP address lookup. Since each incoming packet should be forwarded in wire-speed, it is essential to provide the high-speed search performance. In this paper, IP address lookup algorithms using binary search are studied. Most of the binary search algorithms do not provide a balanced search, and hence the required number of memory access is excessive so that the search performance is poor. On the other hand, binary-search-on-range algorithm provides high-speed search performance, but it requires a large amount of memory. This paper shows an optimized binary-search-on-range structure which reduces the memory requirement by deleting unnecessary entries and an entry field. By this optimization, it is shown that the binary-search-on-range can be performed in a routing table with a similar or lesser number of entries than the number of prefixes. Using real backbone routing data, the optimized structure is compared with the original binary-search-on-range algorithm in terms of search performance. The performance comparison with various binary search algorithms is also provided.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.4
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• pp.539-544
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• 2011

Balanced binary sequences of period $2^n-1(n{\geq}1)$ having the two-valued autocorrelation function have many applications in spread-spectrum communications system. In this paper we propose new nonlinear binary sequences which are constructed from Legendre sequences with the same cross-correlation as the sequences proposed by Cho. These sequences include the m-sequences, GMW sequences, Kasami sequences and No sequences which are described in terms of the trace function over a finite field. Also the proposed sequences have more low cross-correlation distribution than the quadratic form sequences proposed by Klapper.

• 한국정보교육학회:학술대회논문집
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• 2011.01a
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• pp.253-259
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• 2011

Computers are playing a major role in generating, sharing, and utilizing knowledge, which can be recognized as an essential component of national competitiveness. This may lead to the necessity as well as importance of computer education in elementary education. In the paper, we first investigate the necessity of teaching principles of binary system and then we figure out the status quo of teaching the subject in elementary classrooms. Based on the observations in the field, we design learning contents that can be used effectively in classroom so that students can learn easily the fundamental concept of binary system.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.