• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.359-362
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• 2002

In this paper, we propose a new feature-based text watermarking for the binary text image. The structure of specific characters from preprocessed text image are modified to embed watermark. Watermark message are embedded and detected by the following method; Hole line disconnect using the connectivity of the character containing a hole, Center line shift using the hole area and Differential encoding using difference of flippable score points. Experimental results show that the proposed method is robust to rotation and scaling distortion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.23-33
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• 1996

This paper deals with the design of a recursively-indexed binary code for facsimile soruces and its performance. Sources used here are run-lengths of white pixels form higher-resolution facsimile. The modified huffman code used for G.3 facsimile is chosen for the performance comparison. Experiments confirm the fact that recursive indexing preserves the entropy of a memoryless geometric source: the entropy of recursively-indexed physical surce iwth roughly geometric distributin remains within 2% of the empirical source entropy. The designed recursively-indexed binary codes consist of a code applied to text-type documents and to graphics - type documents is compared iwth that of the modified huffman code. Numerical resutls show that the modified huffman code performs well for text-type documents and not equally well for graphics-tyep documents. On the other hand, recursively-indexed binary codes have shown a better performance for graphics-type documents whose distribution are similar to a geometric distribution. Specifically, the code rates of recursively-indexed binary codes with 60 codewords are from 8% to 20% of the empirical source entropy smaller than that of th emodified huffman code with 91 codewords.

• International journal of advanced smart convergence
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• v.1 no.1
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• pp.27-33
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• 2012

In this paper, we analyze and simulate performance of space time block coded (STBC) binary pulse amplitude modulation-direct sequence (BPAM-DS) ultra-wideband (UWB) systems with double binary turbo code in indoor environments for various ubiquitous healthcare (u-healthcare) applications. Indoor wireless channel is modeled as a modified Saleh and Valenzuela (SV) model proposed as a UWB indoor channel model by the IEEE 802.15.SG3a in July 2003. In the STBC encoding process, an Alamouti algorithm for real-valued signals is employed because UWB signals have the type of real signal constellation. It is assumed that the transmitter has knowledge about channel state information. From simulation results, it is shown that the STBC scheme does not have an influence on improving bit error probability performance of the BPAM-DS UWB systems. It is also confirmed that the results of this paper can be applicable for u-healthcare applications.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.39 no.7
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• pp.757-764
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• 1990

The purpose of this study is to process binary images of Breadth First Linear Quadtree in hardware. Inthis paper, we designed and verified logic level circuit of ASIC for the encoding part of the binary image that is to convert the binary image into the representation of the Breadth First Linear Quadtree. The logic level circuit is composed of cells in TTL library. The significance of thes study is to implement an algorithm by hardware rather than by software, so that the processing time can be reduced by about 20 times.

• Journal of the Korean Association of Geographic Information Studies
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• v.25 no.4
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• pp.32-48
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• 2022

This study presented a spatial data serialization technique that can efficiently store and transmit large amounts of spatial data for precision road maps was designed and implemented. For efficient serialization, a binary spatial data structure is defined, and a coordinate value encoding technique without loss of information is designed using the Zigzag-Z-order curve. The spatial data serialization technique designed for precision road maps was tested, and the data size and encoding/decoding speed after encoding were compared with Protocol buffer and Geobuff. As a result, it was confirmed that the designed serialization method was excellent in data weight reduction performance and encoding speed. However, the decoding speed was inferior to other serialization techniques in linestring and polygon type spatial data. Through this study, it was confirmed that spatial data can be efficiently encoded, stored, and transmitted using binary serialization techniques.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.771-777
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• 2012

This paper proposes a binary arithmetic encoder of CABAC using a Common Operation Unit including the three modes. The binary arithmetic encoder performing arithmetic encoding and renormalizer can be simply implemented into a hardware architecture since the COU is used regardless of the modes. The proposed binary arithmetic encoder of CABAC includes Context RAM, Context Updater, Common Operation Unit and Bit-Gen. The architecture consists of 4-stage pipeline operating one symbol for each clock cycle. The area of proposed binary arithmetic encoder of CABAC is reduced up to 47%, the performance of proposed binary arithmetic encoder of CABAC is 19% higher than the previous architecture.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2542-2547
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• 2005

In this paper, we propose a support vector machine (SVM) hyper and kernel parameter optimization method which is based on minimizing radius/margin bound which is a kind of estimation of leave-one-error. This method uses dynamic encoding algorithm for search (DEAS) and gradient information for better optimization performance. DEAS is a recently proposed optimization algorithm which is based on variable length binary encoding method. This method has less computation time than genetic algorithm (GA) based and grid search based methods and better performance on finding global optimal value than gradient based methods. It is very efficient in practical applications. Hand-written letter data of MNI steel are used to evaluate the performance.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.169-176
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• 2003

Genetic algorithm (GA), which has a powerful searching ability and is comparatively easy to use and also to apply, is in the spotlight in the field of the optimization for mechanical systems these days. However, it also contains some problems of slow convergence and low efficiency caused by a huge amount of repetitive computation. To improve the processing efficiency of repetitive computation, some papers have proposed paralleled GA these days. There are some cases that mention the use of gray code or suggest using gray code partially in GA to raise its slow convergence. Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. A binary gray code with n digits corresponds to a hamiltonian path on an n-dimensional hypercube (including direction reversals). The term gray code is open used to refer to a reflected code, or more specifically still, the binary reflected gray code. However, according to proposed reports, gray code GA has lower convergence about 10-20% comparing with binary code GA without presenting any results. This study proposes new Full gray code GA (FGGA) applying a gray code throughout all basic operation fields of GA, which has a good data processing ability to improve the slow convergence of binary code GA.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.111-113
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• 2006

DEAS is an direct searching and optimization method that based on the binary code space. It can be classified as an direct hill climbing searching. However, because of binary code space based searching, the searching in low resolution has random property. As the resolution of code increases during the search, its property of searching changes like that of hill climbing search. This paper propose a method for improving the performance of minimum seeking ability of DEAS with history information. The cost evaluation is increased. However the minimum searching ability of DEAS is improved along the same starting resolution.