• Journal of the Korean Magnetics Society
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• v.12 no.3
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• pp.103-108
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• 2002

We investigated magnetoresistance(MR) and exchange bias properties by annealing in top and bosom type spin valves (SV) with nano-oxide layers (NOL). In top SVs with NOL, MR ratio of 9.2% is obtained after postdeposition annealing at 250$\^{C}$. In bottom SVs with NOL, MR ratio of 10.1 % is obtained after postdeposition annealing at 250$\^{C}$. Therefore, specular reflection of the NOL in bottom SVs is higher than that of the NOL in top SVs. Exchange biasing of bottom SVs with NOL is 28% higher than that of bottom SVs without NOL after annealing. This enhancement of exchange biasing is thought to be due to the reduced magnetic moment of the pinned layer with NOL and enhanced (111) FeMn texture.

• Proceedings of the Korean Magnestics Society Conference
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• 2007.05a
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• pp.160.2-160.2
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• 2007

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1982-1984
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• 2002

The admittance of one-port electrostatic actuator are modeled using the steady-state sinusoidal response. Also the admittance of the differential type actuator is derived taking the practical conditions into consideration, although it has no admittance in ideal case. It is a function of biasing error, driving error, and capacitive mismatch including parasitic capacitors. The validity of the admittance model is proved by comparing between the modeled and measured admittances. The distortion in the frequency response curve measured by a capacitive sensor is analyzed and it is concluded that the admittance is the main cause of this distortion.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.579-582
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• 2000

In this paper, new linearization technique for bipolar OTAs using exponential-law circuits is described. The core circuit of the proposed OTAs is the multi-TANH doublet. The OTAs have adaptively biasing current sources, which consists of the exponential-law circuits. Three types of the OTAs are presented. The linear input voltage ranges of the OTAs are almost the same as the multi-TANH triplet. Further, the OTAs have lower power dissipation than the multi-TANH triplet.

• Proceedings of the Korean Magnestics Society Conference
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• 2005.12a
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• pp.150-151
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• 2005

• Proceedings of the Korean Magnestics Society Conference
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• 2008.12a
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• pp.67.1-67.1
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• 2008

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.974-984
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• 2000

A CMOS voltage driver circuit for voltage down converter is proposed. An adaptive biasing technique is used to enhance load regulation characteristics. The proposed driver circuit uses the NMOS transistor as a driving transistor, so it does not suffer from large Miller capacitances which is one of the problems with conventional PMOS driving transistor, and hence achieves good phase margin and stable frequency response. No additional complex circuit for frequency compensation such as compensation capacitor is required in this implementation. For the same current capability, the size of NMOS transistor in driver circuit is smaller than that of PMOS counterpart. So the smaller die area can be achieved. The circuits is implemented using a 0.8 ${\mu}{\textrm}{m}$ CMOS process and has a die area of 150 ${\mu}{\textrm}{m}$ x 360 ${\mu}{\textrm}{m}$. Proposed circuit has a quiescent power of 60 . In the current driving range from 100 $mutextrm{A}$ to 50 ㎃, load regulation of 5.6 ㎷ is measured.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.5
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• pp.508-514
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• 2013

Substrate integrated waveguide(SIW) constructed by two metal planes and conductive vias in a dielectric substrate, have all the conductors connected each other and hence, cannot be biased by DC sources. We propose a new folded corrugated substrate integrated waveguide(FCSIW) that can be DC-biased. Since the proposed FCSIW replaces the SIW conducting vias by folded open subs, it can supply the DC sources. The FCSIW has better transmission characteristics and 30 % less width than the common corrugated substrate integrated waveguide(CSIW) having a serious leakage generation problem. The FCSIW shows better insertion loss(1.49 dB) compared with that(3.08 dB) of the CSIW measured for 154 mm length devices and averaged at 9~15 GHz frequency band. No leakage has been observed from crosstalk measurements of the FCSIW.