• 한국소음진동공학회논문집
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• 제19권11호
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• pp.1177-1183
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• 2009

The effects of biasing magnetic fields on the performances of magnetostrictive ultrasonic transducers are investigated. The transducers are patch-type ones which are used for SHM of plate structures. Various kinds of configurations of biasing magnets are covered experimentally. It is experimentally verified that how the biasing magnetic field deploys is the most significant factors on maximizing the transducer output. From the magnetostriction curve of nickel, it is concluded qualitatively that it is not the absolute values of biasing magnetic field but the slope of magnetostriction curve to be taken account of.

• 전기전자학회논문지
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• 제26권1호
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• pp.119-123
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• 2022

본 논문은 추가 기생 바이폴라 BJT로 인해 높은 홀딩전압을 갖는 ESD 보호소자에 Self-Biasing 구조를 추가하여 12V 급 어플리케이션에 적합한 새로운 ESD 보호소자를 제안한다. 제안된 소자의 동작원리와 전기적 특성 검증을 위해 Synopsys사의 TCAD Simulation을 사용하여 current density simulation과 HBM simulation을 수행하였고 추가된 Self-Biasing 구조 동작을 확인하였다. Simulation 결과 제안된 ESD 보호소자는 기존의 ESD 보호소자와 비교하여 높은 수준의 홀딩전압을 갖는 것을 확인하였고 이는 듀얼구조로 인한 높은 면적효율과 12V급 어플리케이션에서 충분한 래치업 면역 특성을 가질 것으로 기대된다.

• ETRI Journal
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• 제35권2호
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.168-172
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• 2005

In this paper, we present a new adaptive biasing scheme for CMOS op-amps. The designed circuit has been used in an Operational Transconductance Amplifier (OTA) with ${\pm}1$ V power supply, and it has improved the positive and negative slew rates from 2.92 V/msec to 1242 V/msec and from 1.56 V/msec to 133 V/msec respectively, while maintaining all the small-signal performance parameter values the same as that without adaptive biasing (as expected), however, there was a marginal decrease of the dynamic range. The most useful features of the proposed circuit are that it uses a very low number of components (thus not creating severe area penalty) and requires only 25 nW of extra stand-by power.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Journal of Multimedia Information System
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• 제8권2호
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• pp.143-146
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• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• 센서학회지
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• 제33권1호
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• pp.12-17
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• 2024

Floating inverter amplifiers (FIAs) have recently garnered considerable attention owing to their high energy efficiency and inherent resilience to input common-mode voltages and process-voltage-temperature variations. Since the voltage gain of a simple FIA is low, it is typically cascaded or cascoded to achieve a higher voltage gain. However, cascading poses stability concerns in closed-loop applications, while cascoding limits the output swing. This study introduces a gain-enhanced FIA that features cross-coupled body biasing. Through simulations, it is demonstrated that the proposed FIA designed using a 28-nm complementary metal-oxide-semiconductor technology with a 1-V power supply can achieve a high voltage gain (> 90 dB) suitable for dynamic open-loop applications. The proposed FIA can also be used as a closed-loop amplifier by adjusting the amount of positive feedback due to the cross-coupled body biasing. The capability of achieving a high gain with minimum-length devices makes the proposed FIA a promising candidate for low-power, high-speed sensor interface systems.

• 전기학회논문지
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• 제56권1호
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• pp.132-138
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• 2007

Carbon nanotubes (CNTs) arc grown on Ni catalysts employing an inductively-coupled plasma chemical vapor deposition (ICP-CVD) method. The structural and field-emissive properties of the CNTs grown are characterized in terms of the substrate-bias applied. Characterization using the various techniques, such as field-omission scanning electron microscopy (FESEM), high-resolution transmission electron microscopy (HRTEM), Auger spectroscopy (AES), and Raman spectroscopy, shows that the structural properties of the CNTs, including their physical dimensions and crystal qualities, as well as the nature of vertical growth, are strongly dependent upon the application of substrate bias during CNT growth. It is for the first time observed that the provailing growth mechanism of CNTs, which is either due to tip-driven growth or based-on-catalyst growth, may be influenced by substrate biasing. It is also seen that negatively substrate-biasing would promote the vertical-alignment of the CNTs grown, compared to positively substrate-biasing. However, the CNTs grown under the positively-biased condition display a higher electron-emission capability than those grown under the negatively-biased condition or without any bias applied.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.36-37
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• 2006

Both negative and positive substrate bias effects on the structural properties and field-emission characteristics are investigated. carbon nanotubes (CNTs) are grown on Ni catalysts employing an inductively-coupled plasma chemical vapor deposition (ICP-CVD) method. Characterization using various techniques, such as field-emission scanning electron microscopy (FESEM), high-resolution transmission electron microscopy (HRTEM), Auger spectroscopy (AES), and Raman spectroscopy, shows that the physical dimension as well as the crystal quality of CNTs grown can be changed and controlled by the application of substrate bias during CNT growth. It is for the first time observed that the prevailing growth mechanism of CNTs, which is either due to tip-driven growth or based-on-catalyst growth, may be influenced by substrate biasing. It is also seen that negative biasing would be more effectively role in the vertical-alignment of CNTs compared to positive biasing. However, the CNTs grown under the positively bias condition display much better electron emission capabilities than those grown under negative bias or without bias. The reasons for all the measured data regarding the structural properties of CNTs are discussed to confirm the correlation with the observed field-emissive properties.

• 한국전자파학회논문지
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• 제24권11호
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• pp.1091-1097
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• 2013

이 논문은 $0.11{\mu}m$ RF CMOS 공정에서 비대칭 몸체 바이어싱을 적용한 비교기를 사용한 정류기를 제안한다. 제안하는 정류기는 MOSFET와 두 개의 비교기로 이루어져 있다. 이 비교기는 부하 전압이 입력 전압보다 높을 때 생기는 역방향 누설 전류를 줄이는 데 사용한다. 비대칭 몸체 바이어싱을 사용함으로써 비교기의 High에서 Low 상태로 바꾸는 기준 전압을 높이고, 누설 전류가 흐르는 시간을 줄인다. 13.56 MHz의 2 Vpp 교류전압을 입력하고, $1k{\Omega}$의 저항과 1 nF의 커패시터를 부하에 연결한 환경에서 측정하였다. 시뮬레이션 결과, 전압 변환 효율은 87.5 %, 전력 변환 효율은 45 %이고, 측정한 전압 변환 효율은 85.215 %, 전력 변환 효율은 50 %이다.