• 한국전기전자재료학회논문지
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• 제16권3호
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• pp.247-252
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• 2003

In this paper, we made four types of metal particle $Al_2$O$_3$ barrier reactors with and without dielectric of BaTiO$_3$ between metal particle and $Al_2$O$_3$ barrier to investigate NOx removal characteristic and the effect of dielectric on Nox removal. And Nox removal rate is measured when sludge pellets are put at down stream of plasma reactor. Nox removal rate in the reactor with $Al_2$O$_3$ barrier is much better than that in the reactor without $Al_2$O$_3$ barrier, Nox removal rate is not so good in metal particle-Al$_2$O$_3$ barrier reactor with BaTiO$_3$ between metal particle and $Al_2$O$_3$ barrier, however, Nox removal rate is about 40% in metal particle-Al$_2$O$_3$ barrier reactor with TiO$_2$. The most of NO is conversed to NO$_2$ in these kind of reactor. When sludge pellets are put at down stream of plasma reactor, Nox removal rate is greatly improved up to 90%. It indicates that sludge pellets have great effect on the NO$_2$ removal and the improvement of Nox removal rate, however, dielectric materials between metal particle and $Al_2$O$_3$ barrier have not effect. Organic materials included in sludge may react with NO$_2$ and ozone so that Nox removal rate is greatly improved.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.179-180
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• 2007

반도체의 최소 회로 선폭이 감소함에 따라 Contact 저항이 크게 증가하게 된다. Contact 저항을 낮추기 위하여 Tungsten Metal Contact을 일반적으로 사용하며, Si 기판과의 Ohmic 접촉 및 WF6의 Fluorine과 Si 반응을 억제하기 위한 Barrier Metal로 Ti/TiN 이중막을 사용한다. 본 논문에서는 90nm급 이하 제품의 CVD Ti/TiN Barrier Metal이 유발하는 불량 현상과 원인 규명에 대하여 연구하였으며, Ohmic Contact형성을 위해 TiSix형성 최적화 방안에 대해 정리하였다.

• 전자공학회논문지A
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• 제30A권7호
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• pp.47-59
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• 1993

16M DRAM 용 Al/Si contact 의 열적안정성을 개선하기 위하여 "stuffed" TiN/Ti diffusion barrier를 사용하였다. Diffusion barrier 로서의 특성을 개선하기 위한 Al 증착전 TiN/Ti barrier metal의 열처리 과정중 barrier metal의 두께, 열처리온도, 분위기 등을 변화시켰다. 질소분위기하에서 450도에서 TiN(900A)/Ti(300A) 박막을 열처리 하여 "stuffed" barrier metal을 형성 시켰을 경우 Al 원자의 TiN층으로의 확산의 600도에서 후속열처리한 경우 일어났으나, 700도까지도 Al-spike를 관찰할 수 없었다. 그러나 "stuffed" barrier metal을 550도에서 형성한 경우에는 600도의 후속열처리온도에서 Al이 Si 기판으로 침투했음을 관찰하였다. 박막의 두께를 얇게한 경우, 600도의 후속 열처리에서 Al-spike가 형성되었음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제13권5호
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.985-987
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• 2004

A plastic substrate for flexible display is developed. The gas barrier property in the substrate is improved through depositing metal and metal oxide multi layer on plastic film by PVD process. The metal/metal-oxide multiplayer on plastic film shows excellent gas barrier property and optical property.

• Journal of Information Display
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• 제13권2호
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Applied Science and Convergence Technology
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• 제26권1호
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• pp.16-19
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• 2017

A thin metal layer of molybdenum is placed between the conventional barrier layer and the stainless steel substrate for investigating the diffusion property of iron (Fe) atoms. In this study, the protection probability was confirmed by measuring the concentration of out-diffused Fe using a SIMS depth profile. The Fe concentration of chromium (Cr) barrier layer with 10 nm molybdenum (Mo) layer is 5 times lower than that of Cr barrier without the thin Mo layer. The insertion of a thin Mo metal layer between the barrier layer and the stainless steel substrate effectively protects the out-diffusion of Fe atoms.

• 전자공학회논문지D
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• 제34D권5호
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• pp.61-66
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• 1997

In this paper we report the fabrication of an InGaAs metal-semiconductor-metal (MSM) photodiode(PD) which an InAlAs barrier enhancement layer that has very low dark current and high speed chracteristics. The detector using Cr/Au schottky metal fingers with 4um spacing on a large active area of 300*300um$^{2}$ offers a low dark current of 38nA at 10V, a low capacitance of 0.8pF, and a high 3-dB bandwidth of 2.4 GHz. To our knowledge, these characteristics are better than any previously published results obtained from large area InGaAs MSM PD's. The RC equivalent model and frequency domain current response model considering transit time were also used to analyze the frequency characteristic of the fabricated device.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.97-98
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• 2009

Tunneling barrier engineered charge trap flash (TBE-CTF) memory capacitor were fabricated using the tunneling barrier engineering technique. Variable oxide thickness (VARIOT) barrier and CRESTED barrier consisting of thin $SiO_2$ and $Si_3N_4$ dielectrics layers were used as engineered tunneling barrier. The charge trapping characteristic with different metal gates are also investigated. A larger memory window was achieved from the TBE-CTF memory with high workfunction metal gate.