• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.50-57
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• 1998

In this paper, we propoe a log N-stage ATM concentator. ATM concentrator is used in the ATM access network to concentrate the traffic offered at UNI, so that high utilization of the newtork rewources is achieved. The concetrator may be used as a construction block in the design of ATM switch. We define abasic element, named equalizer, and decribe its function and theory to construct an efficient concentrator using the element. In addition, a control scheme to enhance the concentrator to a superconcentrator is presented, which enables the concentration to start from an arbitrary output. This scheme makes it possible to construct an efficient ditributior or a barrel shifter which are often used in ATM switch and other application. The proposed concentrator has a low hardware complexity of O(N log N), thus it is economical to implement. Also, the time complexity of proposed concentrator for determining the rouging is O(N log N), which is faster than that of the existing ones.

• The Transactions of the Korea Information Processing Society
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• v.1 no.1
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• pp.99-104
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• 1994

This paper proposes the method to process many pattern data 2-dimensionally at high speed in designing the physical of LSI. And this study shows that the switching network,which transmits pattern data between memory and processing elements at high speed on bidirection,has been designed using the barrel shifter and simulated with VHDL design system.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2296-2298
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• 1998

In this paper, an on-chip learning pulse-mode digital neural network with a massively parallel yet compact and flexible network architecture is suggested. Algebraic neural operations are replaced by stochastic processes using pseudo-random sequences and simple logic gates are used as basic computing elements. Using Back-propagation algorithm both feed-forward and learning phases are efficiently implemented with simple logical gates. RNG architecture using LFSR and barrel shifter are adopted to avoid some correlation between pulse trains. Suggested network is designed in digital circuit and its performance is verified by computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1252-1262
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• 1988

This paper describes a functional-level design and simulation of Graphics Processor(GP) which can be used in various graphics systems. GP is divided into two parts: One is CPU, and the other is the interface to I/O peripherals. In order to achieve fast execution of graphics instructions, the CPU has special ALU, barrel shifter and window comparator and a FIFO for instruction prefetch. I/O part controls the DRAM and VRAM which constitute the GP's local memory, generates the signals to drive monitor, and communicates with the host processor. The functional simulation of CPU was done on Daisy workstation while the I/O part was designed using GENESIL, a silicon compiler.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of IKEEE
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• v.17 no.3
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• pp.352-359
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• 2013

This paper proposes an entropy coding unit for H.264/AVC baseline profile. Entropy coding requires code tables for macroblock encoding. There are patterns in codewords of each code tables. In this paper, the patterns between codewords are analyzed to reduce the hardware cost. The entropy coding unit consists of Exp-Golomb unit and CAVLC unit. The Exp-Golomb unit can process five code types in a single unit. It can perform Exp-Golomb processing using only two adders. While typical CAVLC units use various code tables which require large amounts of resources, the sizes of the tables are reduced to about 40% or less of typical CAVLC units using relationships between table elements in the proposed CAVLC unit. After the Exp-Golomb unit and the CAVLC unit generate code values, the entropy unit uses a small size shifter for bit-stream generation while typical methods are barrel shifters.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.53-58
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• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.