• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 1999.03b
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• pp.18-21
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• 1999

In this study in order to make doubly-curved sheet metal effectively a sheet metal forming process has been developed by adopting the flexibility of the incremental forming process and the principle of bending deformation which causes slight deformation to thickness The developed process is an unconstrained forming process with no holder. For this study the experimental equipment is set up with the punch-set which consists of two pairs of lower support-punches and one upper center-punch. In the experiments using aluminum sheet it is found that the curvature of the formed sheet metal is determined by controlling the distance between supporting punches in pairs and the forming depth of the center-punch. and the edge-forming method is proposed for forming the sheet metal into the balanced shape. The equation using process variables such as the distance between supporting punches in pairs and the forming depth of the center-punch is proposed for the prediction of the radii of curvatures of the formed shape and it is corrected by the experimental results and the FEM simulation results about whether springback takes place. It is found that according o the simulation there is a certain set of the distance between a pair of supporting punches and the forming depth of the center-punch which causes a little springback. It is thus shown that the radii of curvatures of the formed sheet metal can be predicated by the corrected equation unless significant springback occurs.

• ETRI Journal
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• v.33 no.3
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• pp.344-354
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• 2011

In this paper, a model is introduced named double relation chains (DRC) based on ordered sets. It is proved that using DRC and special relationships among the members of an alphabet, vectors of this alphabet can be stored and searched in a tree. This idea is general; however, one special application of DRC is the longest prefix matching (LPM) problem in an IP network. Applying the idea of DRC to the LPM problem makes the prefixes comparable like numbers using a pair of w-bit vectors to store at least one and at most w prefixes, where w is the IP address length. This leads to good compression performance. Based on this, two recently introduced structures called coded prefix trees and scalar prefix trees are shown to be specific applications of DRC. They are implementable on balanced trees which cause the node access complexity for prefix search and update procedures to be O(log n) where n is the number of prefixes. As another advantage, the number of node accesses for these procedures does not depend on w. Additionally, they need fewer number of node accesses compared to recent range-based solutions. These structures are applicable on both IPv4 and IPv6, and can be implemented in software or hardware.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Kyungpook Mathematical Journal
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• v.54 no.1
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• pp.95-101
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• 2014

An n-tuple ($a_1,a_2,{\ldots},a_n$) is symmetric, if $a_k$ = $a_{n-k+1}$, $1{\leq}k{\leq}n$. Let $H_n$ = {$(a_1,a_2,{\ldots},a_n)$ ; $a_k$ ${\in}$ {+,-}, $a_k$ = $a_{n-k+1}$, $1{\leq}k{\leq}n$} be the set of all symmetric n-tuples. A symmetric n-sigraph (symmetric n-marked graph) is an ordered pair $S_n$ = (G,${\sigma}$) ($S_n$ = (G,${\mu}$)), where G = (V,E) is a graph called the underlying graph of $S_n$ and ${\sigma}$:E ${\rightarrow}H_n({\mu}:V{\rightarrow}H_n)$ is a function. The restricted super line graph of index r of a graph G, denoted by $\mathcal{R}\mathcal{L}_r$(G). The vertices of $\mathcal{R}\mathcal{L}_r$(G) are the r-subsets of E(G) and two vertices P = ${p_1,p_2,{\ldots},p_r}$ and Q = ${q_1,q_2,{\ldots},q_r}$ are adjacent if there exists exactly one pair of edges, say $p_i$ and $q_j$, where $1{\leq}i$, $j{\leq}r$, that are adjacent edges in G. Analogously, one can define the restricted super line symmetric n-sigraph of index r of a symmetric n-sigraph $S_n$ = (G,${\sigma}$) as a symmetric n-sigraph $\mathcal{R}\mathcal{L}_r$($S_n$) = ($\mathcal{R}\mathcal{L}_r(G)$, ${\sigma}$'), where $\mathcal{R}\mathcal{L}_r(G)$ is the underlying graph of $\mathcal{R}\mathcal{L}_r(S_n)$, where for any edge PQ in $\mathcal{R}\mathcal{L}_r(S_n)$, ${\sigma}^{\prime}(PQ)$=${\sigma}(P){\sigma}(Q)$. It is shown that for any symmetric n-sigraph $S_n$, its $\mathcal{R}\mathcal{L}_r(S_n)$ is i-balanced and we offer a structural characterization of super line symmetric n-sigraphs of index r. Further, we characterize symmetric n-sigraphs $S_n$ for which $\mathcal{R}\mathcal{L}_r(S_n)$~$\mathcal{L}_r(S_n)$ and $$\mathcal{R}\mathcal{L}_r(S_n){\sim_=}\mathcal{L}_r(S_n)$$, where ~ and $$\sim_=$$ denotes switching equivalence and isomorphism and $\mathcal{R}\mathcal{L}_r(S_n)$ and $\mathcal{L}_r(S_n)$ are denotes the restricted super line symmetric n-sigraph of index r and super line symmetric n-sigraph of index r of $S_n$ respectively.

• Korean Journal of Food Science and Technology
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• v.47 no.5
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• pp.608-614
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• 2015

Four Korean commercial rice wines of diverse sensory properties were hedonically rated by 41 consumers. Each rice wine was paired with the selection from six widely popular compatible foods such as kimchi-jjigae, dotori-muk muchim, tteok-galbi, beoseot-jeongol, satae pyeonyuk, and haemul pajeon, and consumers were asked to rate the ideal match of each pair of four rice wines and six compatible foods by using a structured, 12-cm 'just right' line scale. Hedonic ratings of wines were additionally measured after intake of the food-wine pairs. Flavor matches of rice wines with strong ginseng, medicinal, and earthy flavor (JK) or with intense grain and sweet flavor (HS) were significantly higher compared to wines with fruity (SS) or mild-balanced (BS) flavor. The preference for HS wine, which ideally matched satae pyeonyuk, increased most significantly after intake of satae pyeonyuk, while the SS wine that matched ideally with kimchi jjigae did not show any significant increase in preference after intake of kimchi jjigae. Matching wines with food does not negatively affect the preference for the wine; rather, intake of a wine-food pairing increases the overall preference for rice wine.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.84-92
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• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.