• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.168-171
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• 2010

본 논문에서는 GaN HEMT 소자를 이용한 고출력 고효율 특성을 가지는 광대역 SSPA의 개발을 다루고 있다. 개발한 SSPA는 8W 급과 15W 급의 GaN HEMT 소자를 사용하여 Pre-Drive 증폭단을 구성하였으며, Drive 증폭단은 50W/150W급 GaN HEMT 소자를 직/병렬구조로 사용하였다. Main 증폭단은 4-way 분배기와 결합기를 이용한 Balanced Structure를 적용하여 높은 출력을 구현하였으며, 안정적인 동작을 위하여 음(-)전원 제어 회로와 출력신호 검출 회로를 포함하고 있다. 제작된 SSPA의 사용가능 대역은 2.9GHz~3.3GHz로 단일전원을 사용하고 있으며 100us 펄스 폭, 10% Duty Cycle 조건에서 60dB의 전압이득, 1kW 출력과 약 28% 효율 특성을 가지는 것으로 측정되었다. 본 논문에서 개발한 SSPA는 S-대역을 사용하는 레이더시스템의 송신단에 적용될 수 있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.919-923
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• 2003

In this paper, a double-sided planar balun using Microstrip-to-CPW coupled structure is fabricated and measured. The measured amplitude and phase imbalance are, respectively, less than 0.2 dB and 2.1$^{\circ}$ in a wide frequency range from 2.44 GHz to 4.33 GHz. It is expected that the proposed balun can improved the performance of balanced mixer, amplifier and feeding network of antennas. Also, it can be used in many microwave multilayer structures due to its structural characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.5
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• pp.688-693
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• 1999

This paper presents a very simple coupled line structure for MMIC which uses stacked microstrip line and does not employ any dielectric process step. For the analysis and optimization of these coupled line structure, HP-Momentum was used. The measured performance of 3 dB coupler shows 23 to 45 GHz broadband characteristics. Additionally, a balanced 2-stage Ka-Band power amplifier which uses the proposed 3 dB coupler, was also fabricated.

• Journal of the Korean Institute of Telematics and Electronics
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• v.7 no.2
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• pp.21-25
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• 1970

A Possibility of improving the temperature behavior by the use of a balanced diode compensation circuit in a Digital to Analogue converter is studied. Better linearity is achieved by eliminating the ladder network for the summation by means of an operational amplifier. Speed Consideration are taken to achieve 1.5 mesa bits per second with more than 80% useful plateau.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.