• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.237-239
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• 1983

본 논문은 어떤 비동기적인 제어계가 상태 천이도(transition diagram)로 표현되기만 하면 이 입력으로부터 직접 비동기 순차회로를 구성 할 수 있는 알고리즘을 제시하고 있다. 이로써 비동기 회로를 쉽게 하드웨어로 실현 할수 있도록 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1613-1621
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• 1997

Many studies on internal data expression to process logic functions efficiently on computer have been doing actively. In this paper, we propose an efficient logic function manipulation system made on the Objected-Oriented manner, where Binary Decision Diagrams(BDD's) are adopted for internal data espressionof logic functions. Thus it is easy to make BDD's presenting combinational problems. Also, we propose a method of applying filtering function for reducing the size of BDD's instead of attributed bits, and add it to the mainpultion system. As a resutls, the space of address is expanded so that the number of node that can be used in the mainpulation system is increased up to 2/sup 27/. Finally, we apply the implemented system to One-Shot state assignment problems of asynchronous sequential circuits and show that it is efficient for the filtering method to reduce the size of BDD's.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.82-87
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• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• Journal of the Korean Institute of Intelligent Systems
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• v.22 no.1
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• pp.49-55
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• 2012

Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.