• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• Journal of the Korea Institute of Military Science and Technology
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• v.15 no.5
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• pp.676-686
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• 2012

This paper presents a sensor bias estimation method with serial fusion for asynchronous multisensory systems. Serial fusion processes the sensor measurements in a first-come-first-serve basis and it plays an essential role in asynchronous fusion in practice. The proposed algorithm generates the bias measurements using fusion estimates and sensor measurements for bias estimation, and compensates the sensor biases in fusion tracks. A simulation study indicates that the proposed algorithm has the superior performance in bias estimation and accurate tracking.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.93-99
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• 2011

A PRT vehicle's control method is presented in this paper. In the asynchronous vehicle control system, vehicles follow their leading vehicles. Leading vehicles are defined differently among the different types of track. The main topic of this paper is to present a method to define the leading vehicle among different types of track and the calculation algorithm of the safety length the following vehicle must maintain. Simulation program is developed using the algorithm and the results of the test run are presented. An asynchronous PRT vehicle control algorithm was presented by Szillat in the paper "A low level PRT Microsimulation, Dissertation, University of Bristol, 2001". But it is different from the algorithm in this paper. In the algorithm proposed by Markus, vehicles in the merging track are controlled synchronously, and its safety distance between the leading and the following car is evaluated after the establishment of the complicated future time-location table instead of simple equations proposed in this paper.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.11
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• pp.47-52
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• 2015

This paper derives the problems that occur when asynchronous transfer in case of phase, frequency, voltage between the emergency generator and the grid and proposed the countermeasure to solve this problem when the transfer switch replace ATS(Automatic Transfer Switch) with CTTS(Closed Transition Transfer Switch) for the non-interrupting switching. In order to simulate above cases, modelling was used the transient analysis program PSCAD/EMTDC. By using this, the customer installed emergency generator and the grid was implemented. We compared three cases of asynchronous transition based on the basic case and proposed improvement by controlling the governor of emergency generator.

• Journal of Internet Computing and Services
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• v.4 no.5
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• pp.51-60
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• 2003

Asynchronous iteration is a way to reduce performance degradation of some parallel algorithms due to load imbalance or transmission delay between computing nodes, which requires asymmetric communication between the nodes of different speeds. To implement such asynchronous communication on distributed memory systems, we suggest an MPMD method that creates an additional separate server process on each computing node, and compare it with an SPMD method that creates a single process per node.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.1
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• pp.361-378
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• 2012

Most of the current frequency hopping (FH) based dynamic spectrum access (DSA) methods concern a reactive channel access scheme with synchronous inter-channel spectrum sensing, i.e., FH is reactively triggered by the primary user (PU)'s return reported by spectrum sensing, and the PU channel to be switched to is assumed precisely just sensed or ready to be sensed, as if the inter-channel spectrum sensing moments are synchronous. However, the inter-channel spectrum sensing moments are more likely to be asynchronous, which risks PU suffering more interference. Moreover, the spectrum sensing is usually erroneous, which renders the problem more complex. To address this problem, we propose a proactive FH based DSA method against both erroneous spectrum sensing and asynchronous inter-channel spectrum sensing (moments). We term it as proactive DSA. The optimal FH sequence is obtained by dynamic programming. The complexity is also analyzed. Finally, the simulation results confirm the effectiveness of the proposed method.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.1
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• pp.61-67
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• 2014

Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a $4{\times}4$ multiplier logic designed using 0.11um technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.