• Journal of Power Electronics
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• v.8 no.1
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• pp.81-90
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• 2008

This paper presents an investigation of a voltage and frequency controller for an isolated asynchronous generator (IAG) driven. by a wind turbine and supplying 3-phase 4-wire loads to the isolated areas where a grid is not accessible. The control strategy is based on the indirect current control of the VSC (voltage source converter) using the frequency PI controller. The proposed controller consists of three single-phase IGBT (Insulated Gate Bipolar Junction Transistor) based VSC, which are connected to each phase of the IAG through three single phase transformers and a battery at their DC link. The controller has the capability of controlling reactive and active powers to regulate the magnitude and frequency of the generated voltage, harmonic elimination, load balancing and neutral current compensation. The proposed isolated system is modeled and simulated in MATLAB using Simulink and PSB (Power System Block-set) toolboxes to verify the performance of the controller.

• Journal of Power Electronics
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• v.9 no.6
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• pp.874-883
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• 2009

This paper deals with an integrated voltage and frequency (VF) controller for isolated asynchronous generators (IAG) driven by a constant power pico-hydro uncontrolled turbine feeding three-phase four-wire loads. The proposed VF controller is used to control the frequency and voltage of an IAG with load leveling. Such a VF controller is also known as an integrated electronic load controller (IELC) which is realized using an isolated star/polygon transformer with a voltage source converter (VSC) and a battery at its DC bus. The proposed generating system with a VFC is modeled and simulated in MATLAB along with Simulink and Simpower system (SPS) toolboxes. The simulated results are presented to demonstrate the performance of an isolated asynchronous generator feeding three-phase four-wire loads with neutral current compensation.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.67-74
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• 2004

Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.

• Journal of Power Electronics
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• v.10 no.5
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• pp.538-547
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• 2010

This paper deals with a stand-alone wind energy conversion system (WECS) with an isolated asynchronous generator (IAG) and voltage and frequency (VF) control feeding three-phase four-wire loads. The reference generator currents are estimated using the instantaneous symmetrical component theory to control the voltage and frequency of an IAG system. A three-leg voltage source converter (VSC) with an isolated star/delta transformer is used as an integrated VSC. An integrated VSC with a battery energy storage system (BESS) is used to control the active and reactive powers of the WECS. The WECS is modeled and simulated in MATLAB using the Simulink and the Sim Power System (SPS) toolboxes. The proposed VF controller functions as a voltage and frequency regulator, a load leveler, a load balancer and a harmonic eliminator in the WECS. A comparison is made on the rating of the VSC with and without ac capacitors connected at the terminals of an IAG. Simulation and test results are presented to verify the control algorithm.

• International Journal of Contents
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• v.1 no.1
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• pp.21-28
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• 2005

This paper is about the hardness of Leader Election problem in asynchronous distributed systems in which processes can crash but links are reliable. Recently, the hardness of a problem encountered in the systems is defined with respect to the difficulty to solve it despite failures: a problem is easy if it can be solved in presence of failures, otherwise it is hard [9]. It is shown in [9] that problems are classified as three classes: F (fault-tolerant), NF (Not fault-tolerant) and NFC (NF-completeness). Among those, the class NFC is the hardest problem to solve. It is also shown in [9] that the construction of Perfect Failure Detector (problem P) belongs to NFC. In this paper, we show that Leader Election is also one of NFC problems by using a general reduction protocol that reduces the Leader Election Problem to P. We use a formulation of the Leader Election problem as a prototype to show that it belongs to NFC.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1432-1435
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• 1996

This paper obtains maximum allowable delay bounds for stability of network-based control systems and presents a network scheduling method which makes the network-induced delay be less than the maximum allowable delay bound. The maximum allowable delay bounds are obtained using the Lyapunov theorem. Using the network scheduling method, the bandwidth of a network can be allocated to each node and the sampling period of each sensor and controller can be determined. The presented method can handle three kinds of data (periodic, real-time asynchronous, and non real-time asynchronous data) and guarantee real-time transmissions of real-time synchronous data and periodic data, and possible transmissions of non real-time asynchronous data. The proposed method is shown to be useful by examples in two types of network protocols such as the token control and the central control.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.1
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• pp.1-8
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• 1979

This paper describes a simple asynchronous time dime division multiplexing system developed by means of a synchronous delta modulation. In realizing asynchronous multlplexlng system time author deals with a technique of multiplexing communication channels by reversing the polarity of output pulse and superimposing the channels at a certain time Interval. The results of experiments on the number of error pulses, signal-to-noise ratio and frequency characteristics have shown fair agreements with the theoretically predicted ones related to the system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.2
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• pp.22-26
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• 1974

To synthesize transition-sensitive asynchronous sequential circuits, D-type transition-sensitive flip-flop is used.4 new concept, a pair of input state is introduced and used to reduce the number of internal states. We proposed an algorithm to synthesize multiple-input change asynchronous sequential circuits directly from a primitive state table an6 demonstrated the method is better than the one which is due to Bredeson and Hulina and Others.