• 전기학회논문지
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• 제58권12호
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• pp.2484-2491
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• 2009

This paper proposes robust state feedback control of asynchronous sequential machines with model uncertainty. The considered asynchronous machine is deterministic, but its state transition function is partially known before executing a control process. The main objective is to derive the existence condition for a corrective controller for which the behavior of the closed-loop system can match a prescribed model in spite of uncertain transitions. The proposed control scheme also has learning ability. The controller perceives true state transitions as it undergoes corrective actions and reflects the learned knowledge in the next step. An adaptation is made such that the controller can have the minimum number of state transitions to realize a model matching procedure. To demonstrate control construction and execution, a VHDL and FPGA implementation of the proposed control scheme is presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.1724-1727
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• 2002

Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

• 한국군사과학기술학회지
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• 제15권5호
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• pp.676-686
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• 2012

This paper presents a sensor bias estimation method with serial fusion for asynchronous multisensory systems. Serial fusion processes the sensor measurements in a first-come-first-serve basis and it plays an essential role in asynchronous fusion in practice. The proposed algorithm generates the bias measurements using fusion estimates and sensor measurements for bias estimation, and compensates the sensor biases in fusion tracks. A simulation study indicates that the proposed algorithm has the superior performance in bias estimation and accurate tracking.

• 전기학회논문지
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• 제60권1호
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• pp.93-99
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• 2011

A PRT vehicle's control method is presented in this paper. In the asynchronous vehicle control system, vehicles follow their leading vehicles. Leading vehicles are defined differently among the different types of track. The main topic of this paper is to present a method to define the leading vehicle among different types of track and the calculation algorithm of the safety length the following vehicle must maintain. Simulation program is developed using the algorithm and the results of the test run are presented. An asynchronous PRT vehicle control algorithm was presented by Szillat in the paper "A low level PRT Microsimulation, Dissertation, University of Bristol, 2001". But it is different from the algorithm in this paper. In the algorithm proposed by Markus, vehicles in the merging track are controlled synchronously, and its safety distance between the leading and the following car is evaluated after the establishment of the complicated future time-location table instead of simple equations proposed in this paper.

• ETRI Journal
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• 제33권5호
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• 조명전기설비학회논문지
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• 제29권11호
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• pp.47-52
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• 2015

This paper derives the problems that occur when asynchronous transfer in case of phase, frequency, voltage between the emergency generator and the grid and proposed the countermeasure to solve this problem when the transfer switch replace ATS(Automatic Transfer Switch) with CTTS(Closed Transition Transfer Switch) for the non-interrupting switching. In order to simulate above cases, modelling was used the transient analysis program PSCAD/EMTDC. By using this, the customer installed emergency generator and the grid was implemented. We compared three cases of asynchronous transition based on the basic case and proposed improvement by controlling the governor of emergency generator.

• 인터넷정보학회논문지
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• 제4권5호
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• pp.51-60
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• 2003

비동기 반복 알고리즘은 부하 불균형 및 컴퓨터 노드 간의 전송 지연에 의한 병렬 알고리즘의 성능 저하를 완화하는 하나의 방법인데, 이는 노드들 간의 비대칭적 데이터 전송을 필요로 한다 본 논문에서는 분산 메모리 시스템 상에서 MPMD 방식으로 노드당 별도의 서버 프로세스를 추가로 생성하여 비대칭적 전송을 구현하고, 노드당 하나의 프로세스를 생성하는 SPMD 방식과 비교하며 그 장단점에 대해 논의한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제6권1호
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• pp.361-378
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• 2012

Most of the current frequency hopping (FH) based dynamic spectrum access (DSA) methods concern a reactive channel access scheme with synchronous inter-channel spectrum sensing, i.e., FH is reactively triggered by the primary user (PU)'s return reported by spectrum sensing, and the PU channel to be switched to is assumed precisely just sensed or ready to be sensed, as if the inter-channel spectrum sensing moments are synchronous. However, the inter-channel spectrum sensing moments are more likely to be asynchronous, which risks PU suffering more interference. Moreover, the spectrum sensing is usually erroneous, which renders the problem more complex. To address this problem, we propose a proactive FH based DSA method against both erroneous spectrum sensing and asynchronous inter-channel spectrum sensing (moments). We term it as proactive DSA. The optimal FH sequence is obtained by dynamic programming. The complexity is also analyzed. Finally, the simulation results confirm the effectiveness of the proposed method.

• 한국산업정보학회논문지
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• 제19권1호
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• pp.61-67
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• 2014

센서 시스템과 같은 저전력 설계를 요구하는 시스템에서 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation), 노화 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서, 신뢰할 수 있는 초저전력 설계에서 비동기 회로가 스케일링 이슈를 해결할 수 있는 방법으로 최근 다시 고려되고 있다. 그러나, 디지털 시스템에서 동기회로를 NCL 회로로 모두 대체하는 것은 쉽지가 않기때문에 동기회로와 비동기 회로 사이의 연결이 꼭 필요하다. 본 논문에서는 동기회로와 비동기 회로를 연결할 수 있는 새로운 설계방법을 보이고, 0.18um 공정기술을 사용한 $4{\times}4$ 곱셈기를 사용해서 검증을 하였다.

• 대한전자공학회논문지SD
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• 제40권3호
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• pp.33-42
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• 2003

본 논문에서는 NST (new Svoboda-Tung) 알고리즘을 이용한 비동기식 제산기의 효율적 설계에 관해 기술한다. 본 제산기설계에서는 비동기 설계방식을 사용하여 제산연산이 필요할 때에만 동작함으로써 전력소모를 줄이도록 설계한다. 제산기는 비동기식 파이프라인 구조를 이용한 per-scale부, iteration step부, on-the-fly converter부의 세부분으로 구성된다. Per-scale부에서는 새로운 전용 감산기를 이용하여 적은 면적과 고성능을 갖도록 설계한다. Iteration step부에서는 4개의 division step을 갖는 비동기식 링 구조로 설계하고, 아울러 크리티컬 패스(critical path)에 해당하는 부분만을 2선식으로, 나머지 부분은 단선식으로 구성하는 구현방법을 채택하여 하드웨어의 오버헤드를 줄인다. On-the-fly converter부는 iteration step부와 병렬연산이 가능한 on-the-fly 알고리즘을 이용하여 고속연산이 되도록 설계한다. 0.6㎛ CMOS 공정을 이용하여 설계한 결과, 1,480 ×1,200㎛²의 면적에 12,956개의 트랜지스터가 사용되었고, 41.7㎱의 평균지연시간을 가졌다.