• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.4
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• pp.655-660
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• 2024

Relay has been applied various communication environments due to its advantages of performance enhancement in communication systems. In this paper, we analyze the performance of a dual-hop communication system which uses one relay by considering asymmetric communication scenarios. The performance is based on bit error rate. Firstly, we compare the overall performance of dual-hop communication system under symmetric and asymmetric, and then analyze the performance depending on the resource allocation. Energy allocation and relay location are considered in the resource allocation. The performance of overall system for each energy allocation and relay location is analyzed. In addition, we analyze the performance of communication system when both energy and relay location are considered simultaneously. Based on the analyzed performance, we discuss the effect of resource allocation for symmetric and asymmetric environments.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.43-51
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• 2021

As the number of mobile devices has been increasing tremendously, system capacity should be enlarged in future next generation communication, such as the fifth-generation (5G) and beyond 5G (B5G) mobile networks. For such future networks, non-orthogonal multiple access (NOMA) has been considered as promising multiple access technology. In this paper, to reduce both latency and complexity in existing NOMA, we propose non-successive interference cancellation (SIC) NOMA with asymmetric binary pulse amplitude modulation (2PAM), nearly without bit-error rate (BER) loss. First, we derive the closed form of BER expressions for non-SIC NOMA with asymmetric 2PAM, especially under Rayleigh fading channels. Then, it is shown that the BER performance of the stronger channel user who is supposed to perform SIC in conventional NOMA can be nearly achieved by the proposed non-SIC NOMA with asymmetric 2PAM, especially without SIC. Furthermore, we also show that the BER performance of the weaker channel user in conventional NOMA can be more closely achieved by the proposed non-SIC NOMA with asymmetric 2PAM. These BERs are shown to be achieved over the part of the power allocation range, which is consistent with the NOMA principle of user fairness. As a result, the non-SIC NOMA scheme with asymmetric 2PAM could be considered as a promising NOMA scheme toward next generation communication.

• International journal of advanced smart convergence
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• v.9 no.4
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• pp.34-41
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• 2020

Nowadays, the advanced smart convergences of the artificial intelligence (AI) and the internet of things (IoT) have been more and more important, in the fifth generation (5G) and beyond 5G (B5G) mobile communication. In 5G and B5G mobile networks, non-orthogonal multiple access (NOMA) has been extensively investigated as one of the most promising multiple access (MA) technologies. In this paper, we investigate the achievable data rate for the asymmetric binary pulse amplitude modulation (2PAM), in non-orthogonal multiple access (NOMA). First, we derive the closed-form expression for the achievable data rate of the asymmetric 2PAM NOMA. Then it is shown that the achievable data rate of the asymmetric 2PAM NOMA reduces for the stronger channel user over the entire range of power allocation, whereas the achievable data rate of the asymmetric 2PAM NOMA increases for the weaker channel user improves over the power allocation range less than 50%. We also show that the sum rate of the asymmetric 2PAM NOMA is larger than that of the conventional standard 2PAM NOMA, over the power allocation range larger than 25%. In result, the asymmetric 2PAM could be a promising modulation scheme for NOMA of 5G systems, with the proper power allocation.

• Journal of Internet Computing and Services
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• v.4 no.5
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• pp.51-60
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• 2003

Asynchronous iteration is a way to reduce performance degradation of some parallel algorithms due to load imbalance or transmission delay between computing nodes, which requires asymmetric communication between the nodes of different speeds. To implement such asynchronous communication on distributed memory systems, we suggest an MPMD method that creates an additional separate server process on each computing node, and compare it with an SPMD method that creates a single process per node.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.11
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• pp.5338-5359
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• 2017

In-band full-duplex (IBFD) wireless communication supports symmetric dual transmission between two nodes and asymmetric dual transmission among three nodes, which allows improved throughput for distributed IBFD wireless networks. However, inter-node interference (INI) can affect desired packet reception in the downlink of three-node topology. The current Half-duplex (HD) medium access control (MAC) mechanism RTS/CTS is unable to establish an asymmetric dual link and consequently to suppress INI. In this paper, we propose a medium access control mechanism for use in distributed IBFD wireless networks, FD-DMAC (Full-Duplex Distributed MAC). In this approach, communication nodes only require single channel access to establish symmetric or asymmetric dual link, and we fully consider the two transmission modes of asymmetric dual link. Through FD-DMAC medium access, the neighbors of communication nodes can clearly know network transmission status, which will provide other opportunities of asymmetric IBFD dual communication and solve hidden node problem. Additionally, we leverage FD-DMAC to transmit received power information. This approach can assist communication nodes to adjust transmit powers and suppress INI. Finally, we give a theoretical analysis of network performance using a discrete-time Markov model. The numerical results show that FD-DMAC achieves a significant improvement over RTS/CTS in terms of throughput and delay.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.219-224
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• 2015

Recently, the multi-core processor architecture is widely used in the digital signal processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multi-core processors are known to have higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core digital signal processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric quad-core, octa-core and hexadeca-core digital signal processors and compared with the symmetric ones of similar hardware budget using UTDSP benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.3
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• pp.163-169
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• 2014

Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.233-238
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• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.157-163
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• 2016

If trace-driven or execution-driven simulation is used for the performance analysis of asymmetric multi-core processors, excessive time and much disk space are necessary. In this paper, statistical simulations are performed for asymmetric multi-core processors with various hardware configurations. For the experiment, SPEC 2000 benchmark programs are used for profiling and synthesis, which is supplied as input for the simulation of asymmetric multi-core processors. As a result, the performance of asymmetric multi-core processor obtained by statistical simulation is comparable to that of the trace-driven simulation with a tremendous reduction in the simulation time.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.3
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• pp.361-369
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• 2018

This paper proposes a design of asymmetric time division multiple access method for tactical radio communication. Typical tactical radio communication has a limited execution of transmission, because uplink message requires more extended response time than downlink message. In order to solve this problem, this paper analyzes operational environment of Korean tactical radio communication and proposes an asymmetric TDMA based on it for performance of tactical communication. The simulation model is used to investigate constraints of real experiments for proving effectiveness of the proposed approach. Simulations results show that the proposed scheme outperforms the conventional scheme in terms of throughput, response time, and delay.