• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• The Transactions of the Korea Information Processing Society
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• v.4 no.3
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• pp.811-820
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• 1997

Disk arrays are using to enhance data trandfer rate and I/O performance in multimedia applications which need a high-performance storage device with large storage capacity and high-speed network.As performance varies with configuration and data layout scheme,disk array characteristic variables must be approrpriately deter-mined in desibning disk array archetecture for a speciffic applicatoin. In this paper,in order to design a disk array architecturte as a storage server of a small-scale VOD system,we evaluate performance of a disk array to chose the number of disks in the array,disk array cinfiguration,a degree of declustering for a given data block size of continous media file system and I/D request size through simulation.Simulation result shows that RAID level 5 with 5 disks ios a suitable candidate for the disk array architecture which privides MPEG-2 files with a rate of 6 Mbps,Moreover,we whow that stripe unit is 64 KB and a layout scheme is contigous placement.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.6
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• pp.389-397
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• 2015

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of $100{\times}100mm^2$ with 0.5 mm interval) to 87.5% (scanning of $200{\times}200mm^2$ with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

• Transactions of Materials Processing
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• v.18 no.4
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• pp.310-316
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• 2009

Micro lens array(MLA) is widely used in information technology(IT) industry fields for various applications such as a projection display, an optical power regulator, a micro mass spectrometer and for medical appliances. Recently, MLA have been fabricated and developed by using a reflow method having the processes of micro etching, electroplating, micro machining and laser local heating. Laser thermal relaxation method is introduced in marking of microdots on the surface of densified glass. In this paper, we have proposed a new direct fabrication process using UV laser local thermal-expansion(UV-LLTE) and investigated the optimal processing conditions of MLA on the surface of negative photo-resist material. We have also studied the 3D shape of the micro lens obtained by UV laser irradiation and the optimal process conditions. And then, we made chrome mold by electroplating. After that, we made MLA using chrome mold by hot embossing processing. Finally, we have measured the opto-physical properties of micro lens and then have also tested the possibility of MLA applications.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.293-296
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• 2007

In this paper, we propose the systolic array architecture for the vector median filter. In the color image processing, the vector signal (i.e. the color) consists of three elements, red, green and blue. The vector median filter is very effective to utilize the correlation among red, green and blue elements. The computational complexity of the proposed architecture for computing the vector median of N vector signals is (N+2) clock periods compared to the (3N+1) clock periods in the previous method. In addition to, the input vector signals can be loaded in serial in the proposed architecture. In the previous method, N input vector signals should be loaded to the vector median filter in parallel at the first clock. The proposed architecture is implemented with FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1164-1170
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• 2011

In this paper, we propose accurate lattice extraction of elemental image array and pre-processing methods in computational integral imaging. Pre-processing methods remove distortions and noises of the image. Such distortions occurred in pickup systems are rotational errors. Distortions will degrade the resolution of reconstructed images. To overcome this problem, we propose our methods for extraction of elemental image array and pre-processing methods. Also, we describe that distortions affect the high quality reconstruction. Optical and computational experiments indicate that reconstructed images applied our methods is better than reconstructed images unapplied our methods.

• Journal of the Korea Society of Computer and Information
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• v.17 no.10
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• pp.107-116
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• 2012

The applying of semantic technologies that aim to let computers understand and automatically process the meaning of the interlinked data on the Web is spreading. In Semantic Web, understanding and accessing the associations between data that is, the meaning between data as well as accessing to the data itself is important. W3C recommended RDF (Resource Description Framework) as a standard format to represent both Semantic Web data and their associations and also proposed several RDF query languages in order to support query processing for RDF data. However further researches on the query language definition considering the semantic associations and query processing techniques are still required. In this paper, using the suffix array-based indexing scheme previously introduced for RDF query processing, we propose a query processing approach to handle ${\rho}$-path query which is the representative type of semantic associations. To evaluate the query processing performance of the proposed approach, we implemented two different types of query processing approaches and measured the average query processing times. The experiments show that the proposed approach achieved 1.8 to 2.5 and 3.8 to 11 times better performance respectively than others two.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.277-280
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• 2002

This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04b
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• pp.1237-1240
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• 2001

최근 제품의 초소화와 반도체의 고집적화로, 작은 크기로 많은 리드를 제공하기 위해, 부품 밑면에 격자형태로 볼이 배열되어 있는 BGA나 CSP부품들이 최근 많이 이용되고 있다. 하지만, BGA는 한번 PCB에 장착되면, 볼 외관검사가 원천적으로 불가능하므로, 부품을 장착하기 전에 볼 품질의 검사와 부품의 정밀한 위치 및 각도의 측정이 요구된다. 본 논문에서는 BGA부품의 위치 및 각도를 추출하기 위한 방법과 볼을 검사하기 위한 알고리즘을 소개한다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.