• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.302-309
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• 2004

The transmission capacity of wireless communication systems may become dramatically high by employ multiple transmit and receive antennas with space-time coding techniques appropriate to multiple transmit antennas. For large number of transmit antennas and at high bandwidth efficiencies, the receiver may become too complex whenever correlation across transmit antennas is introduced. Reducing decoding complexity at receiver by combining array processing and space-time codes (STC) helps a communication system using STC to overcome the big obstacle that prevents it from achieving a desired high transmission rate. Multi-carrier CDMA (MC-CDMA) allows providing good performance in a channel with high inter-symbol interference. Antenna array, STC and MC-CDMA system have a similar characteristic that transmit-receive data streams are divided into sub-streams. Thus, there may be a noticeable reduction of receiver complexity when we combine them together. In this paper, the combination of array processing and STC in MC-CDMA system over slow selective-fading channel is investigated and compared with corresponding existing MC-CDMA system using STC. A refinement of this basic structure leads to a system design principle in which we have to make a trade off between transmission rate, decoding complexity, and length of spreading code to reach a given desired design goal.

• 한국전자파학회논문지
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• 제16권7호
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• pp.740-745
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• 2005

본 논문은 GSM 시스템의 다경로 환경에서 선형 제약형 어레이 처리기를 이용하여 주종형 어레이 처리와 공간 유화 방법으로 원하는 신호를 추정하는 성능에 대하여 논한다. SINR과 BER 성능에서 주종형 어레이 처리방법과 공간유화 방법이 선형 제약형 어레이 처리방법보다 우수한 반면, 공간 유화 방법의 성능이 주종형 어레이 처리기 보다 더 나은 것으로 나타났다.

• 정보학연구
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• 제10권3호
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• 센서학회지
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• 제24권6호
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• pp.368-372
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• 2015

In this paper, we proposed a post-processing technique for improving classification performance of electronic nose (E-Nose) system which may be occurred drift signals from sensor array. An adaptive radial basis function network using stochastic gradient (SG) and singular value decomposition (SVD) is applied to process signals from sensor array. Due to drift from sensor's aging and poisoning problems, the final classification results may be showed bias and fluctuations. The predicted classification results with drift are quantized to determine which identification level each class is on. To mitigate sharp fluctuations moving-averaging (MA) technique is applied to quantized identification results. Finally, quantization and some edge correction process are used to decide levels of the fluctuation-smoothed identification results. The proposed technique has been indicated that E-Nose system was shown correct odor identification results even if drift occurred in sensor array. It has been confirmed throughout the experimental works. The enhancements have produced a very robust odor identification capability which can compensate for decision errors induced from drift effects with sensor array in electronic nose system.

• 전기의세계
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• 제29권9호
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• pp.584-593
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• 1980

Conventional radar antenna systems are susceptible to performance degradation caused by unwanted signals received via the antenna sidelobes and/or mainlobes. Adaptive array systems offer possible solution to this interference problem by automatically steering nulls to unwanted signals providing significant system performance improvement. Another important andvantage of the adaptive array is its self-optimization capability which uses the collective incoming noise data for the nulling purposes. This paper provides a tutorial introduction to adaptive arrays as well as some new development of recent research in this area. Optimum link between the antenna theory and signal processing has been sought by illustrating the gain patterns and output signal-to-noise ratio. Signal acqusition methods are shown including a new attempt of the use of spread-spectrum techniques in conjuction with array systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2547-2549
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• 1998

Automatic yield-test equipment for micro mirror array using image processing was developed. This computerized test equipment can classify the error states of the micromirrors. The test results are displayed on the monitor as a map which shows the error states and position. It is possible to measure yield and reliability with this test equipment for micromirror array using image processing.

• 전자공학회논문지C
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• 제34C권10호
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• pp.36-42
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• 1997

In the whole world, the research about the VLSI implementation of motion estimation algorithm is progressed to actively full (brute force) search algorithm research with the development of systolic array possible to parallel and pipeline processing. But, because of processing time's limit in a field to handle a huge data quantily such as a high definition television, many problems are happened to full search algorithm. In the paper, as a fast processing to using parallel scheme for the serial input image data, motion estimator of systolic array structure verifying that processing time is improved in contrast to the conventional full search algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.14-16
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• 1988

With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

• 전자공학회논문지S
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• 제34S권10호
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• 융합신호처리학회논문지
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• 제4권3호
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• pp.61-67
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• 2003

We propose a systolic array for dynamic programming which is a technique for solving combinatorial optimization problems. We derive a systolic array for single source shortest path Problem, SA SSSP, and then show that the systolic array serves as dynamic Programming systolic array which is applicable to any dynamic programming problem by developing a systolic array for 0 1 knapsack problem, SA 01KS, with SA SSSP for a basis. In this paper, each of SA SSSP and SA 01KS is modeled and simulated in RT level using VHDL, then synthesized to a schematic and finally implemented to a layout using the cell library based on 0.35${\mu}{\textrm}{m}$ 1 poly 4 metal CMOS technology.