• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.97-102
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• 2020

This paper relates with the Hybrid-SE-MMA (Signed-Error MMA) that is possible to improving the equalization performance by using the adaptive modulus and adaptive step size in SE-MMA adaptive equalizer for the minimizing the intersymbol interference. The equalizer tap coefficient is updatted use the error signal in MMA algorithm for adaptive equalizer. But the sign of error signal is used for the simplification of arithmetic operation in SE-MMA algorithm in order to updating the coefficient. By this simplification, we get the fast convergence speed and the reduce the algorithm processing speed, but not in the equalization performance. In this paper, it is possible to improve the equalization performance by computer simulation applying the adaptive modulus to the SE-MMA which is proposional to the power of equalizer output signal. In order to compare the improved equalization performance compared to the present SE-MMA, the recovered signal constellation that is the output of the equalizer, residual isi, MD(maximum distortion), MSE and the SER perfomance that means the robustness to the external noise were used. As a result of computer simulation, the Hybrid-SE-MMA improve equalization performance in the residual isi and MD, MSE, SER than the SE-MMA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• Journal of Broadcast Engineering
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• v.16 no.2
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• pp.339-349
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• 2011

IBDI (Internal Bit Depth Increase) is able to significantly improve the coding efficiency of high definition video compression by increasing the bit depth (or precision) of internal arithmetic operation. However the scheme also increases required internal memory for storing decoded reference frames and this can be significant for higher definition of video contents. So, the reference frame memory compression method is proposed to reduce such internal memory requirement. The reference memory compression is performed on 4x4 block called the processing unit to compress the decoded image using the correlation of nearby pixel values. This method has successively reduced the reference frame memory while preserving the coding efficiency of IBDI. However, additional information of each processing unit has to be stored also in internal memory, the amount of additional information could be a limitation of the effectiveness of memory compression scheme. To relax this limitation of previous memory compression scheme, we propose a selective merging-based reference frame memory compression algorithm, dramatically reducing the amount of additional information. Simulation results show that the proposed algorithm provides much smaller overhead than that of the previous algorithm while keeping the coding efficiency of IBDI.

• Journal of IKEEE
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• v.24 no.3
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• pp.901-908
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• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.43-51
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• 2008

In this paper, we are implemented low-power structure for Inter prediction, Intra prediction, Deblocking filter, Transform and Quantization blocks in H.264/AVC Encoder. The proposed Inter/Intra prediction blocks are shown 60.2% cell area reduction by adder reduction through Distributed Arithmetic, 44.3% add operation reduction using MUX for hardware share in Deblocking filter block. Furthermore we applied CSD and CSS process to reduce the cell area instead of multipliers that take a lot of area. The FPGA(Field Programmable Gate Array) and ARM Process based H.264/AVC encoder is implemented using proposed low power IPs. The proposed structure Platforms are implemented to interlock with FPGA and ARM processors. H.264/AVC Encoder implementation using Platforms shows that proposed low-power IPs can use H.264/AVC Encoder SoC effectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.187-192
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• 2014

Various researches are performed to extract significant features from continuous images. The FAST algorithm has the simple structure for arithmetic operation and it is easy to extraction the features in real time. For this reason, the FPGA based hardware accelerator is implemented and widely applied for the FAST algorithm. The hardware accelerator needs the threshold to extract the features from images. The threshold is influenced not only the number of extracted features but also the total execution time. Therefore, the way of threshold control is important to stabilize the total execution time and to extract features as much as possible. In order to control the threshold, this paper proposes the PI controller. The function and performance for the proposed PI controller are verified by using test images and the PI control logic is designed based on Xilinx Vertex IV FPGA. The proposed scheme can be implemented by adding 47 Flip Flops, 146 LUTs, and 91 Slices to the FAST hardware accelerator. This proposed approach only occupies 2.1% of Flip Flop, 4.4% of LUTs, and 4.5% of Slices and can be regarded as a small portion of hardware cost.

• Journal of Educational Research in Mathematics
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• v.23 no.3
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• pp.373-388
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• 2013

This paper is to investigate how two elementary school teacher's belief mathematics as educational content, and teaching and learning mathematics as a part of educational methodology, and what the two teachers believe towards gifted children and their education, and what the classes demonstrate and its effects on the sociomathematical norms. To investigate this matter, the study has been conducted with two teachers who have long years of experience in teaching gifted children, but fall into different belief categories. The results of the study show that teacher A falls into the following category: the essentiality of mathematics as 'traditional', teaching mathematics as 'blended', and learning mathematics as 'traditional'. In addition, teacher A views mathematically gifted children as autonomous researchers with low achievement and believes that the teacher is a learning assistant. On the other hand, teacher B falls into the following category: the essentiality of mathematics as 'non-traditional', teaching mathematics as 'non-traditional, and learning mathematics as 'non-traditional.' Also, teacher B views mathematically gifted children as autonomous researchers with high achievement and believes that the teacher is a learning guide. In the teacher A's class for gifted elementary school students, problem solving rule and the answers were considered as important factors and sociomathematical norms that valued difficult arithmetic operation were demonstrated However, in the teacher B's class for gifted elementary school students, sociomathematical norms that valued the process of problem solving, mathematical explanations and justification more than the answers were demonstrated. Based on the results, the implications regarding the education of mathematically gifted students were investigated.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.33 no.4
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• pp.403-411
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• 2023

Objectives: Formalin is used as an anthelmintic in farms where flounder are raised. In this study, we aim to identify formaldehyde exposure levels for aquaculture industry workers and provide basic data for managing formaldehyde exposure. Methods: Exposure levels of formaldehyde in the air, including formalin spraying operations, were assessed separately for personal and area samples. In addition, considering the formalin administration method, dermal exposure to the hands was estimated when administering the chemical, and dermal exposure to the legs during water tank work was estimated by collecting water in the water tank and evaluating the amount of formaldehyde remaining. Finally, the respiratory exposure level and the estimated dermal exposure level were added to derive the total exposure level and compared with the maximum allowable human dose. Results: As a result of the airborne evaluation, the formaldehyde concentration of the worker (1 person) who performed the formalin spraying and flounder sorting was 33.61 ppb, and the arithmetic mean of formaldehyde concentrations of the workers (3 people) who only performed the flounder sorting was 3.28 ppb (range: 2.25-4.89 ppb). In the case of dermal exposure, when spraying formalin once, the amount was estimated to be 0.33-2.62 mg when wearing protective gear and 3.27-26.12 mg when not wearing it. Conclusions: There was a difference in the formaldehyde exposure level of workers depending on their operation of handling formalin and whether or not protective gear was worn. In particular, because the level of formaldehyde exposure due to dermal exposure can be significant, there is a need to improve formalin administration methods in a way that avoids skin contact as much as possible.