• Journal of Internet Computing and Services
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• v.25 no.1
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• pp.1-8
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• 2024

In the API gateway, API composition is an essential function that can reduce the number of client calls and prevent over-fetching and under-fetching. API composition that operate with IMJ (In-Memory Join) consume a lot of resources, putting a burden on the performance of the API gateway. In this paper, to improve the problem of IMJ-style API composition, we propose SAPIC (Stream-based API Composition), which delivers the data to be composed to the client by streaming. SAPIC calls each MSA API that makes up the client response data and immediately streams the received response data to the client, reducing the resource consumption of the API gateway and providing faster response time compared to IMJ. As a result of a comparison experiment with GraphQL, a representative API combination technology, SAPIC recorded a maximum CPU occupancy rate of approximately 21 to 70 % lower, a maximum heap usage rate of approximately 16 to 74 % lower, and a throughput rate that was 1 to 2.3 times higher than GraphQL.

• Journal of The Korea Institute of Healthcare Architecture
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• v.19 no.4
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• pp.47-60
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• 2013

Purpose: This study examines construction core plans for the users of vertical-typed general hospitals to effectivly use the flow line. Methods: The study sampled representative 9 hospitals, calculated the depth value through Convex Map of Space Syntax and Justified Graph according to the determination of form of construction cire, and analyzed its functional connectivity. Results: The analysis of the connectivity between operation core part and emergency part of core space with high importance in the hospitals showed that the types of hospital and hospital have the lowest depth value in the spatial phase diagram, where central treatment part and outpatient part are arranged well vertically. Elevators for patients at these hospitals are close to operation and emergency parts actually separated from the elevators for passengers. For shortening of flow line of patients and private movement environment, however, it is desirable to arrange the elevators for patients to be adjacent to the operation parts and to arrange the emergent patient entrances more effectively to separate them from the flow line of visitors and guardians. Implications: Consideration should be taken into account for the effective flow line design. This study hopefully may serve as a stepping stone for the standard design of horizontal/vertical flow line.

• Journal of the Korean Institute of Landscape Architecture
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• v.24 no.1
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• pp.97-108
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• 1996

The purposes of this study were to develop a forest landscape assessment technique for landscape ecological planting and urban forest management. The study was conducted by 4 steps in a case of "Inwang Mt.", Seoul. The process and results of the study are as follows : 1. The vegetation types of the Inwang Mt. were identified. 2. The 19 visual types from the vegetation types were classified. 3. The visual preference for the classified types was evaluated. Sorbus alnifolia community, Sorbus alnifolia community-Robinia pseudoacacia group, etc. were highly preferred. 4. A voting distribution graph of each visual type and an ecological -visual assessment map were developed. Finally the applications of the study were suggested.suggested.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.01a
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• pp.173-175
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• 2012

To spread the incredible experience of wandering around a building, we propose the architecture of indoor navigation system based on inter-floor. Firstly, we combine trilateration method with Fingerprint Positioning Algorithm for positioning and Dijkstra Algorithm for calculating paths. Then the system can get the user's current locations and provide relevant paths according to the user's choice. Moreover, it can also provide the navigation path which takes the inter-floor information into consideration. It breaks the traditional navigation based on planar graph and has abundant business value.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.430-432
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• 2004

Multicasting is an efficient means of one to many (or many to many) communications. Due to the frequent and unpredictable topology changes, multicast still remains as challenge and no one-size-fits-all protocol could serve all kinds of needs in ad hoc network. Protocols and approaches currently proposed on this issue could be classified mainly into four categories, tree-based, meshed-based, statelessness and hybrid. In this article, we borrow the concept of Eulerian ring in graph theory and propose a novel ring-based multicast framework--Hierarchical Eulerian Ring-Oriented Multicast Architecture (HEROMA) over wireless mobile Ad hoc network. It is familiar with hybrid protocol based on mesh and tree who concentrates on efficiency and robustness simultaneously. Architecture and recovery algorithm of HEROMA are investigated in details. Simulation result is also presented, which show different level of improvements on end-to-end delay in scenario of small scale.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• KIPS Transactions on Software and Data Engineering
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• v.6 no.3
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• pp.125-134
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• 2017

The SOA (Service Oriented Architecture) based softwares are escalated because of quickly coping with business requirement. SOA can not apply to existing test method because of loosely coupled service and massage exchange architecture. In this paper, we suggest a method of test case generation using BPMN (Business Process Model and Notation). First we model processes, then make Business Flow Graph (BFG). After searching the euler path through symmetrized BFG about input and output degrees, we generate test cases. A method of test case generation using BPMN can apply at SOA-based system, and reduce the number of test cases.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.749-766
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• 2021

Cyber powers around the world are conducting cyber information-gathering activities in cyberspace, a global domain within the Internet-based information environment. Accordingly, it is imperative to obtain the latest information through the cyber intelligence preparation of the battlefield (IPB) process to prepare for future cyber operations. Research utilizing the cyber battlefield visualization method for effective cyber IPB and situation awareness aims to minimize uncertainty in the cyber battlefield and enable command control and determination by commanders. This paper designed architecture by classifying cyberspace into a physical, logical network layer and cyber persona layer to visualize the cyber battlefield using BGP archive data, which is comprised of BGP connection information data of routers around the world. To implement the architecture, BGP archive data was analyzed and pre-processed, and cyberspace was implemented in the form of a Di-Graph. Information products that can be obtained through visualization were classified for each layer of the cyberspace, and a visualization method was proposed for performing cyber IPB. Through this, we analyzed actual North Korea's BGP and OSINT data to implement North Korea's cyber battlefield centered on the Internet network in the form of a prototype. In the future, we will implement a prototype architecture based on Elastic Stack.

• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.