• 제목/요약/키워드: anneal

검색결과 216건 처리시간 0.023초

CMOS 소자를 위한 NiSi의 surface damage 의존성 (The dependence of NiSi for CMOS Technology on Surface Damage)

  • 지희환;배미숙;이헌진;오순영;윤장근;박성형;왕진석
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.167-170
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    • 2002
  • The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

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전하 트랩 형 비휘발성 기억소자를 위한 재산화 산화질화막 게이트 유전악의 특성에 관한 연구 (Characteristics of the Reoxidized Oxynitride Gate Dielectric for Charge Trap Type NVSM)

  • 이상은;박승진;김병철;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 추계학술대회 논문집
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    • pp.37-40
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    • 1999
  • For the first time, charge trapping nonvolatile semiconductor memories with the deoxidized oxynitride gate dielectric is proposed and demonstrated. Gate dielectric wit thickness of less than 1 nm have been grown by postnitridation of pregrown thermal silicon oxides in NO ambient and then reoxidation. The nitrogen distribution and chemical state due to NO anneal/reoxidation were investigated by M-SIMS, TOF-SIMS, AES depth profiles. When the NO anneal oxynitride film was reoxidized on the nitride film, the nitrogen at initial oxide interface not only moved toward initial oxide interface, but also diffused through the newly formed tunnel oxide by exchange for oxygen. The results of reoxidized oxynitride(ONO) film analysis exhibits that it is made up of SiO$_2$(blocking oxide)/N-rich SiON interface/Si-rich SiON(nitrogen diffused tunnel oxide)/Si substrate. In addition, the SiON and the S1$_2$NO Phase is distributed mainly near the tunnel oxide, and SiN phase is distributed mainly at tunnel oxide/Si substrate interface.

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Anneal Temperature Effects on Hydrogenated Thin Film Silicon for TFT Applications

  • Ahn, Byeong-Jae;Kim, Do-Young;Yoo, Jin-Su;Junsin Yi
    • Transactions on Electrical and Electronic Materials
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    • 제1권2호
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    • pp.7-11
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    • 2000
  • a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

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Structural Investigations of $RuO_2$ and Pt ad Films fir the Applications of memory Devices

  • S. M. Jung;Park, Y. S.;D. G. Lim;Park, Y.;J. Yi
    • 한국결정성장학회:학술대회논문집
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    • 한국결정성장학회 1998년도 PROCEEDINGS OF THE 14TH KACG TECHNICAL MEETING AND THE 5TH KOREA-JAPAN EMGS (ELECTRONIC MATERIALS GROWTH SYMPOSIUM)
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    • pp.57-60
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    • 1998
  • Lean zirconate titanate (PZT) is an attractive material for the memory device applications. We have investigated Pt and{{{{ { RuO}_{2 } }}}} as a botton electrode for a device application of PZT thin film. The bottom electrodes were prepared by using an RF magnetron sputtering method. The substrate temperature influenced the resistivity of Pt and {{{{ { RuO}_{2 } }}}} a s well as the film crystal structure. XRD examination shows that a preferred(111) orientations for the substrate temperature of 30$0^{\circ}C$. From the XRD and AFM results, we recommend the substrate temperature of 30$0^{\circ}C$ for the bottom electrode growth. We investigated and anneal temperature effect because Perovskite PZT structure is recommended for the memory device applications and the structural transformation is occurred only after and elevated heat treatment. As post anneal temperature was increased from RT to $700^{\circ}C$, the resistivity of Rt and {{{{ { RuO}_{2 } }}}} w as decreased. Surface morphology was observed by AFM as a function of post anneal temperature.

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Transmission Electron Microscopy Study of Stacking Fault Pyramids Formed in Multiple Oxygen Implanted Silicon-on-Insulator Material

  • Park, Ju-Cheol;Lee, June-Dong;Krause, Steve J.
    • Applied Microscopy
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    • 제42권3호
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    • pp.151-157
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    • 2012
  • The microstructure of various shapes of stacking fault pyramids (SFPs) formed in multiple implant/anneal Separation by Implanted Oxygen (SIMOX) material were investigated by plan-view and cross-sectional transmission electron microscopy. In the multiple implant/anneal SIMOX, the defects in the top silicon layer are confined at the interface of the buried oxide layer at a density of ${\sim}10^6\;cm^{-2}$. The dominant defects are perfect and imperfect SFPs. The perfect SFPs were formed by the expansion and interaction of four dissociated dislocations on the {111} pyramidal planes. The imperfect SFPs show various shapes of SFPs, including I-, L-, and Y-shapes. The shape of imperfect SFPs may depend on the number of dissociated dislocations bounded to the top of the pyramid and the interaction of Shockley partial dislocations at each edge of {111} pyramidal planes.

As 이온 주입된 Si의 결정성 거동에 관한 연구 (A Study of Crystalline Behaviour on $\textrm{As}^{+}$ Ion-Implanted Silicon)

  • 문영희;송영민;김종오
    • 한국재료학회지
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    • 제9권1호
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    • pp.99-103
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    • 1999
  • We investigated the crystalline behavior in active ion implanted silicon through Raman spectroscopy. Four a-Si(amorphous Si) peaks were observed that are related to the ion implantation induced a-Si layer. After the isochronical anneal(30min). and isothermal anneal($450^{\circ}C$), noticeable recovery of crystalline-Si peak at 519cm\ulcorner and peak center shift of the a-Si TO from 465cm\ulcorner to 480cm\ulcorner were observed by RNM(Random Network Model). By applying RNM and SCLM(Spatial Correlation Length Model), the peak center and FWHM(the Full Width at half Maximum) of a-Si were changed dramatically between T\ulcorner=$200^{\circ}C$ and 30$0^{\circ}C$. From the results, it can be said that there is an abrupt structural change at this temperature region.

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고온의 염기성 수용액에서 Ni기 합금의 응력부식파괴

  • 김홍표;황성식;국일현;김정수
    • 한국원자력학회:학술대회논문집
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    • 한국원자력학회 1998년도 춘계학술발표회논문집(2)
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    • pp.84-89
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    • 1998
  • Alloy 600 및 alloy 690과 Ni-8Cr-lOFe 합금 등의 응력부식(stress corrosion cracking, SCC) 거동을 고온의 염기성 분위기에서 C-ring 시편을 사용하여 연구하였다. Alloy 600과 alloy 690을 여러 조건에서 열처리하여 etching한 후 탄화물의 분포와 입계 주변의 Cr고갈 정도 등의 미세조직을 광학현미경과 주사 전자현미경(SEM)으로 관찰하였다. 이들 재료에 대한 SCC 시험을 315$^{\circ}C$의 40% NaOH 수용액에서 일정한 부하전위(부식전위 + 200㎷)를 가하면서 수행하였으며, 동일 조건에서의 분극거동도 측정하였다. Alloy 600 MA(mill anneal) 및 TT(thermal treatment)의 SCC 저항성은 alloy 690 TT와 Ni-8Cr-10Fe SA(solution anneal)보다 낮았다. Alloy 600 TT 재료는 alloy 600 MA 및 SA 재료에 비해 SCC 저항성이 더 컸다. 고용 탄소농도는 alloy 600의 SCC 저항성에 큰 영향을 주지 못했다. 대부분의 Alloy 600은 균열전파 입계균열을 보였으나, 일부에서는 입계 및 입내 혼합양상(mixed mode cracking)을 보였다. 염기성 분위기에서 Ni기 합금의 SCC 거동을 미세조직, 분극거동의 관점에서 고찰하였다.

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저온 화학기상증착법 및 급속가열 공정을 이용한 그래핀의 합성 (Graphene Synthesis by Low Temperature Chemical Vapor Deposition and Rapid Thermal Anneal)

  • 임성규;문정훈;이희덕;유정호;양준모;왕진석
    • 한국전기전자재료학회논문지
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    • 제22권12호
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    • pp.1095-1099
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    • 2009
  • As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.

고온초전도 BSCCO 2223 선재간의 초전도 접합부 제조연구 (Fabrication of superconducting Joints Between PIT Processed BSCCO 2223 Tapes by Single and Multiple Press & reaction Annealing)

  • 유재무;고재웅;정형식
    • 연구논문집
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    • 통권27호
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    • pp.175-181
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    • 1997
  • Superconducting joints between Bi-2223/Ag tapes are fabricated by a press & reaction anneal and a multiple press & anneal. The silver sheath was mechanically or chemically removed from one side of each tape without altering the superconducting core. The exposed superconducting core of the two tapes were brought into contact and pressed so as to form a lap joint. The joined tapes were then subjected to a series of different thermomechanical treatments to achieve optimum heat treatment condition. The result from transport measurements shows that critical current ($I_c$) transmitting through joined area reaches 9A, approximately 60% of the current capacity of the tapes themselves. The critical current through joined area was improved by repeated press and reaction annealing. Measurements of the current-voltage relationship were made with several configuration of the voltage probes to characterize the critical current variation and I-V curve along the joint. Also discussed are microstructural aspects of the superconducting joint.

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