• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.564-572
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• 2008

The performance of the direct adaptive time-delay command shaping filter depends on the select time-delay. In the previously introduced direct adaptive command shaping filter, however, the time-delay value is fixed and only the magnitudes of the impulses are learned. In this paper, the authors introduce a new scheme to adapt the time-delay which is to be used in conjunction with the direct adaptive command shaping for the improved vibration suppression in flexible motion system. In order to formulate the time-delay adaptation scheme, the authors have analyzed the effect of the time-delay value on the performance of the direct adaptive command shaping filter. By modifying the direct adaptation formula based on the analysis result the authors have established a set of equations to adapt the time-delay toward the optimal value. Simulation results show the effectiveness of the proposed time-delay adaptation approach for the improved vibration suppression.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.701-707
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• 1987

This paper is concerned with an accurate delay time modling of the ED MOS logic gates and its application to the multiple delay logic simulator. The proposed delay model of the ED MOS logic gate takes account of the effects of not only the loading conditions but also the slope of the input waveform. Defining delay as the time spent by the current imbalance of the active inverter to charge and discharge the output load, with respect to physical reference levels, rise and fall model delay times are obtained in an explicit formulation, using optimally weighted imbalance currents at the end points of the voltage transition. A logic simulator which uses multiple rise/fall delays based on the model as decribed in the above has been developed. The new delay model and timing verification method are evaluated with repect to delay accuracy and execution time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.895-902
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• 2012

In this paper, we propose a novel equalizer to compensate for the group delay including AM/PM nonlinear distortion characteristics by the nonlinear power amplifier (PA). The group delay characteristic is a nonlinear non-constant time delay that appears differently depending on each frequency component. The phase distortion by AM/PM characteristics arising from the power amplifier is a major factor to increase group delay. By the group delay distortion, the signal in the constellation expands and is rotated. Considering the problem mentioned above, the nonlinear time delay that appears differently depending on each frequency component is classified as a static group delay and AM/PM characteristic of PA, the different phase transitions depending on the size of input signal as a dynamic group delay. Static group delay estimates and compensate for phase distortions in the frequency domain with type-based method and dynamic group delay compensates for phase rotation in the time domain. We confirmed that the group delay compensation techniques were enough to compensate the group delay characteristics including AM/PM characteristics of the power amplifier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1571-1576
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• 2005

DCS has many processing components and various communication elements. And its communication delay characteristic is affected diverse operating situation and context. Especially, binding signal which traversed from one control-node to another control-node undergo all sort of delay conditions. So its delay value has large deviation with the lapse of time, and the measurement of delay statistics during long time is very difficult by using general oscilloscope or other normal instruments. This thesis introduces the design and implementation of PC-based BDAS(Binding Delay Analysis System) System developed to overcomes these hardships. The system has signal-generator, IO-card, data-acquisition module, delay-calculation and analyzer module, those are implemented on industrial standard PC/Ethernet hardware and Windows/Linux platforms. This system can detect accurate whole-system-wide delay time including io, control processing and network delay, in the resolution of msec unit, and can analyze each channel's delay-historic data which is maintained by realtime database. So, this system has strong points of open system architecture, for example, user-friendly environment, low cost, high compatibility, simplicity of maintenance and high extension ability. Of all things, the measuring capability of long-time delay-statistics obtained through historic-DB make the system more valuable and useful, which function is essential to analyze accurate delay performance of DCS system. Using this system, the verification of delay performance of DCS for nuclear power plants is succeeded in KNICS(Korea Nuclear Instrumentation & Control System) projects

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.1-7
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• 2000

This paper studies the delay-characteristics using the singular values and vectors of Hankel operators for input delay systems. First, the computational method of Hankel singular values and their corresponding singular vectors are introduced, and then it is analytically provea that all the Hankel singular vlues have a monotone increasing properties as the length of delay time increases. Furthermore, through a simple numerical example, it is shown that the Hankel singular values are dependent only on the ratio of the time constant of a lumped parameter system to the length of delay , and in case that the time constant is relatively larger than the delay time, the lumped parameter characteristic has a great influence on the input delay systems.

• Journal of Preventive Medicine and Public Health
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• v.26 no.4 s.44
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• pp.650-660
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• 1993

This study aims to describe the causes of medically unnecessary hospital stay at a teaching tertiary hospital, using modified version of Delay Tool in which the causes of delay are divided into slx major categories : delay related to test scheduling, test results, surgery, medical staff, patient/family, and administration. For the analysis of hospital stay, 6,479 inpatient-days were reviewed in two medical and four surgical departments for one month. Initially inappropriate hospital stays were identified using Appropriateness Evaluation Protocol (AEP), and causes of delay listed in Delay Tool were assigned to each of them. In both medical and surgical services, the most important cause of delay was related to medical staffs, ranging from 3.6% to 51.6% of total inpatient days. Next important category was delay related to test scheduling in medical services ($4.7{\sim}9.2%$), and delay related to surgery in surgical services ($7.3{\sim}15.0%$). Among subcategories of delay related to medical staffs, delay due to conservative care was the most important cause of inappropriate hospital stay ($2.9{\sim}6.4%$). Each clinical departments had different distribution among delay categories, which could not be fully justified by their clinical charateristics. The Delay Tool would be helpful in exploring factors related to the inefficient use of hospital beds. As a measurement tool of inappropriate hospital stay, however, the Delay Tool should be refined in the definitions of categories and its contents.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.6
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• pp.719-726
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• 2009

A delay system in fuze for high explosive shell is an important safety device, but failure in the delay system usually causes failure of the shell. Root-cause analysis of failure in the delay system is required since failure in over 10-years stored delay system recently occurs. In this paper, failure in the delay system was reproduced experimentally to examine aged characteristics of the delay system, and the failed delay system shows the same characteristics as ones of failed delay systems in field. Based on the reproduced experiments, accelerated life testings and the data analysis of failure times of delay systems were performed to predict the storage lifetime.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.11-21
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• 1997

The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.