• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.567-572
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• 2004

This paper shudies an automatic gain control(AGC) algorithm used in wireless communication cellular systems. The AGC design includes the selection of the appropriate analog-to-digital converter(ADC) and keeping the input power to the ADC constant to minimize the quantization noise generated from the analog-to-digital conversion process. In this paper the process to determine the required precision or the An is illustrated and the method to set the design parameters of the AGC is proposed. And the validity of the proposed algorithm is verified by computer simulation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.571-573
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• 1988

A new ripple analog-to-digital converter(ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the input signal in two serial steps. First a coarse conversion is made to determine the most significant bits by the first parallel ADC. The results control a switching network to connect the series resistor segment, the analog signal is contained within, to the second parallel ADC. At second step, a fine conversion is made to determine the least signification bits by the second parallel ADC. The circuit requires 2(2$\frac{N}{2}$) comparators, 2(2$\frac{N}{2}$) resistors, and 2(2$\frac{N}{2}$) switches for N-bit resolution.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.522-523
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• 2017

Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.387-400
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• 2017

A new junction-splitting based SAR ADC with a redundant searching capacitor array structure in $0.13{\mu}m$ CMOS process to alleviate capacitor mismatch effects, is presented. The normalized average power has a factor of 0.35 to the conventional SAR ADC at 10-bit conversion accuracy. Statistical experiments show the number of missing codes resulting from the mismatch reduces by 95% for 3% unit-capacitor mismatch ratio, while keeping the conversion energy to that of the conventional JS capacitor array.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1259-1264
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• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.6A
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• pp.425-432
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• 2003

In this paper, we designed a multi-carrier digital transmitter for CDMA base-station using a direct conversion scheme and verified the performance through circuit simulations. We examined a new technology required to design a multi-carrier transmitter, then designed and simulated a multi-carrier digital transmitter. ADS (Advanced Design System), RF simulation S/W of Agilent Technologies, was used for designing and simulating the multi-carrier digital transmitter. First, we simulated a digital block and an analog block separately, then performed a co-simulation for entire system. From the results, the final analog outputs of the designed multi-carrier digital transmitter met the spectrum mask characteristics of IS-97 & 3G TS 25.104 standard requirements. It means that proposed scheme could be applied to implement a multi-carrier digital transmitter for CDMA base-station. Therefore, proposed multi-carrier digital transmitter using a direct conversion scheme can accomplish cost-reduction and improvements of technology in the next CDMA base-station.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2164-2170
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• 2010

Digital Radio Frequency Memory, ( as DRFM ), is a device with the ability to restore output to the input RF signal in the required time after storing the incoming RF signals. Therefore DRFM is widely used in Jammer, EW Simulator, Target Echo Generator, and so on. This paper proposes its hardware implementation composed with the high frequency part and the digital processing part consisting of RF input/output module and local oscillator module. It is also proposed the replicated signal generation method which is consisted of the Analog-Digital conversion in the form of pulsed RF signal quantization, and FPGA to save and produce the playback signal, and RF signals to produce a Digital-Analog Conversion in the digital processing unit. This proposed scheme applied to test board and confirmed the validity of the proposed scheme through the test results obtained by the simulated input signals.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.14-20
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• 1997

Due to several advantages of Pulse Width Modulated(PWM) Converter, such as unity power factor with low-harmonics and energy regeneration, PWM converter has been widely used in industrial application. In every application of energy conversion equipment, the design and implementation must be carried out considering performance and cost. High quality with low cost is the best choice for energy conversion equipment. High dc link voltage can reduce inverter and motor side losses and system dimension compare to low dc link voltage. Analog controller can make PWM converter cheaper without considerable degradation of the performance than digital controller. This paper shows the simplified analog controller-for 600V dc link voltage using stationary reference frame control and the simulation results.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.65-71
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• 2005

Physical signals generated in the real world are transformed into electrical signals through sensors and fed into electronic circuits. The electrical signals input to electronic circuits are in analog form, thus they must be converted to digital signals using an ADC(Analog-Digital Converter) for digital processing. Signal processing circuits and ADCs that are to be integrated on a single chip together with silicon micro sensors should be designed to have less silicon area and less power consumption. This paper proposed a charge redistribution ADC which reduces silicon area considerably. The proposed method achieves 8 bit conversion by performing 4-bit conversion twice. It reduced the area of capacitor array, which takes most of the ADC area, by 1/16 when compared to a conventional method. Though it uses twice the number of clocks as a conventional method, it would be appropriate to be integrated with a silicon pressure sensor on a single chip since it does not demand high conversion rate.

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.561-564
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• 2009

A cryptographic dongle, which is capable of transmitting encrypted voice signals over the CDMA/GSM voice channel, was designed and implemented. The dongle used PIC microcontroller for signals processing including analog to digital conversion and digital to analog conversion, encryption and communicating with the smart phone. A smart phone was used to provide power to the dongle as well as passing the encrypted speech to the smart phone which then transmits the signal to the network. A number of tests were conducted to check the efficiency of the dongle, the firmware programming, the encryption algorithms, and the secret key management system, the interface between the smart phone and the dongle and the noise level.